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Commits on Jan 18, 2018

• [AArch64][GlobalISel] Add isel support for global values in the large code model.

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  787c92d

Commits on Jan 15, 2018

• [GlobalISel][Legalizer] Convert some typedefs to using. NFC.

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  bc98528

Commits on Jan 4, 2018

• Revert "[X86] Regenerate test"

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  0f0caba

• [DAGCombine] Ensure SDNode use iterator is incremented properly.

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  e5c4445

Commits on Jan 3, 2018

• [GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow

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  caeab26

Commits on Jan 2, 2018

• [AArch64][GlobalISel] Fix assert fail with unknown intrinsic.

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  7b20f91

• [AArch64][GlobalISel] Enable GlobalISel at -O0 by default

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  d8de4ce

Commits on Dec 19, 2017

• [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.

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  ea090c0

Commits on Dec 11, 2017

• [GlobalISel] Disable GISel for big endian.

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  4feece4

Commits on Nov 30, 2017

• [GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/stores/args/returns.

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  ff7abc1

Commits on Oct 9, 2017

• [AArch64] Improve codegen for inverted overflow checking intrinsics

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  f78df63

Commits on Oct 8, 2017

• [AArch64][GlobalISel] Add a test case for G_PHI of p0 instruction selection.

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  0c84366

• [AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection.

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  6a8905a

• [AArch64][GlobalISel] Make G_PHI of p0 types legal.

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  d20b82b

Commits on Oct 6, 2017

• [GlobalISel] Fix legalizer trying to process a deleted instruction.

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  0ef919d

Commits on Sep 29, 2017

• [X86] Improve codegen for inverted overflow checking intrinsics.

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  e116340

Commits on Sep 28, 2017

• [X86] Add overflow intrinsic test in preparation for D38161.

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  e5e1c85

Commits on Aug 4, 2017

• [SCEV] Preserve NSW information for sext(subtract).

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  edab1e1

Commits on Jul 13, 2017

• [AArch64] Add an SVE target feature to the backend and TargetParser.

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  51a4b73

Commits on May 19, 2017

• Fix vector pass-through value being unused in IRBuilder::CreateMaskedGather

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  fc4cf8d

Commits on May 16, 2017

• Re-commit r302678, fixing PR33053.

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  f693628

Commits on May 10, 2017

• [AArch64] Enable use of reduction intrinsics.

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  7c631c8

• Add a late IR expansion pass for the experimental reduction intrinsics.

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  0dd30f8

Commits on May 9, 2017

• Introduce experimental generic intrinsics for horizontal vector reductions.

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  8f1f7ce

Commits on May 1, 2017

• Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.

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  195d3fa

Commits on Apr 20, 2017

• [SVE] Fix mismatched sign comparison warning in unit test from r300842.

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  3e9c4ea

• [MVT][SVE] Scalable vector MVTs (3/3)

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  0f69ba8

• [MVT][SVE] Scalable vector MVTs (2/3)

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  0e37006

• [MVT][SVE] Scalable vector MVTs (1/3)

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  780f89d

Commits on Feb 8, 2017

• Revert r294437 as it broke an asan buildbot.

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  3d47c75

• [AArch64][TableGen] Skip tied result operands for InstAlias

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  61d1158

Commits on Nov 8, 2016

• Adds the loop end location to the loop metadata.

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  0a1b0ce

Commits on Nov 7, 2016

• This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.

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  813d120

Commits on Aug 15, 2014

• [AArch64] Narrow arguments passed in wrong position on the stack in

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  cef3ad6

Commits on Jul 25, 2014

• [ARM] Emit ABI_PCS_R9_use build attribute.

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