Skip to content

Commit

Permalink
[cfg] Add PMP parameters to ibex_config.yaml
Browse files Browse the repository at this point in the history 
Also renames configs as part of this as they start to get unweildy if
all features get described in the config name.
  • Loading branch information
@GregAC
GregAC committed May 15, 2020
1 parent 9bd3350 commit 00b46d9
Show file tree
Hide file tree
Showing 10 changed files with 206 additions and 87 deletions.
2 changes: 1 addition & 1 deletion Makefile
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
IBEX_CONFIG ?= small-3cmult
IBEX_CONFIG ?= small

FUSESOC_CONFIG_OPTS = $(shell ./util/ibex_config.py $(IBEX_CONFIG) fusesoc_opts)

Expand Down
6 changes: 3 additions & 3 deletions azure-pipelines.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,6 +154,6 @@ jobs:
- template : ci/ibex-rtl-ci-steps.yml
parameters:
ibex_configs:
- small-3cmult
- experimental-maxperf-1cmult
- experimental-maxperf-bm-1cmult
- small
- experimental-maxperf-pmp
- experimental-maxperf-pmp-bm
41 changes: 36 additions & 5 deletions dv/riscv_compliance/ibex_riscv_compliance.core
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,32 +28,60 @@ parameters:
datatype: int
paramtype: vlogparam
default: 1
description: Enable the M ISA extension (hardware multiply/divide)
description: "Enable the M ISA extension (hardware multiply/divide) [0/1]"

RV32E:
datatype: int
paramtype: vlogparam
default: 0
description: Enable the E ISA extension (reduced register set)
description: "Enable the E ISA extension (reduced register set) [0/1]"

RV32B:
datatype: int
paramtype: vlogparam
default: 0
description: Enable the B ISA extension (bit manipulation EXPERIMENTAL)
description: "Enable the B ISA extension (bit manipulation EXPERIMENTAL) [0/1]"

SRAM_INIT_FILE:
datatype: str
paramtype: vlogdefine
description: "Path to a vmem file to initialize the RAM with"

MultiplierImplementation:
datatype: str
paramtype: vlogparam
description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
default: "fast"

BranchTargetALU:
datatype: int
paramtype: vlogparam
default: 0
description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)"

WritebackStage:
datatype: int
paramtype: vlogparam
default: 0
description: Enables third pipeline stage (EXPERIMENTAL)
description: "Enables third pipeline stage (EXPERIMENTAL)"

PMPEnable:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable PMP"

PMPGranularity:
datatype: int
default: 0
paramtype: vlogparam
description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"

PMPNumRegions:
datatype: int
default: 0
paramtype: vlogparam
description: "Number of PMP regions"

targets:
sim:
Expand All @@ -68,6 +96,9 @@ targets:
- MultiplierImplementation
- BranchTargetALU
- WritebackStage
- PMPEnable
- PMPGranularity
- PMPNumRegions
toplevel: ibex_riscv_compliance
tools:
verilator:
Expand Down
134 changes: 70 additions & 64 deletions dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,9 @@ module ibex_riscv_compliance (
input IO_RST_N
);

parameter bit PMPEnable = 1'b0;
parameter int unsigned PMPGranularity = 0;
parameter int unsigned PMPNumRegions = 4;
parameter bit RV32E = 1'b0;
parameter bit RV32M = 1'b1;
parameter bit RV32B = 1'b0;
Expand Down Expand Up @@ -105,91 +108,94 @@ module ibex_riscv_compliance (
);

ibex_core_tracing #(
.DmHaltAddr(32'h00000000),
.DmExceptionAddr(32'h00000000),
.RV32E(RV32E),
.RV32M(RV32M),
.RV32B(RV32B),
.MultiplierImplementation(MultiplierImplementation),
.BranchTargetALU(BranchTargetALU),
.WritebackStage(WritebackStage)
.PMPEnable (PMPEnable ),
.PMPGranularity (PMPGranularity ),
.PMPNumRegions (PMPNumRegions ),
.RV32E (RV32E ),
.RV32M (RV32M ),
.RV32B (RV32B ),
.MultiplierImplementation (MultiplierImplementation),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.DmHaltAddr (32'h00000000 ),
.DmExceptionAddr (32'h00000000 )
) u_core (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
.clk_i (clk_sys ),
.rst_ni (rst_sys_n ),

.test_en_i ('b0),
.test_en_i ('b0 ),

.hart_id_i (32'b0),
.hart_id_i (32'b0 ),
// First instruction executed is at 0x0 + 0x80
.boot_addr_i (32'h00000000),

.instr_req_o (host_req[CoreI]),
.instr_gnt_i (host_gnt[CoreI]),
.instr_rvalid_i (host_rvalid[CoreI]),
.instr_addr_o (host_addr[CoreI]),
.instr_rdata_i (host_rdata[CoreI]),
.instr_err_i (host_err[CoreI]),

.data_req_o (host_req[CoreD]),
.data_gnt_i (host_gnt[CoreD]),
.data_rvalid_i (host_rvalid[CoreD]),
.data_we_o (host_we[CoreD]),
.data_be_o (host_be[CoreD]),
.data_addr_o (host_addr[CoreD]),
.data_wdata_o (host_wdata[CoreD]),
.data_rdata_i (host_rdata[CoreD]),
.data_err_i (host_err[CoreD]),

.irq_software_i (1'b0),
.irq_timer_i (1'b0),
.irq_external_i (1'b0),
.irq_fast_i (15'b0),
.irq_nm_i (1'b0),

.debug_req_i ('b0),

.fetch_enable_i ('b1),
.core_sleep_o ()
.boot_addr_i (32'h00000000 ),

.instr_req_o (host_req[CoreI] ),
.instr_gnt_i (host_gnt[CoreI] ),
.instr_rvalid_i (host_rvalid[CoreI]),
.instr_addr_o (host_addr[CoreI] ),
.instr_rdata_i (host_rdata[CoreI] ),
.instr_err_i (host_err[CoreI] ),

.data_req_o (host_req[CoreD] ),
.data_gnt_i (host_gnt[CoreD] ),
.data_rvalid_i (host_rvalid[CoreD]),
.data_we_o (host_we[CoreD] ),
.data_be_o (host_be[CoreD] ),
.data_addr_o (host_addr[CoreD] ),
.data_wdata_o (host_wdata[CoreD] ),
.data_rdata_i (host_rdata[CoreD] ),
.data_err_i (host_err[CoreD] ),

.irq_software_i (1'b0 ),
.irq_timer_i (1'b0 ),
.irq_external_i (1'b0 ),
.irq_fast_i (15'b0 ),
.irq_nm_i (1'b0 ),

.debug_req_i ('b0 ),

.fetch_enable_i ('b1 ),
.core_sleep_o ( )
);

// SRAM block for instruction and data storage
ram_1p #(
.Depth(64*1024/4)
) u_ram (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
.req_i (device_req[Ram]),
.we_i (device_we[Ram]),
.be_i (device_be[Ram]),
.addr_i (device_addr[Ram]),
.wdata_i (device_wdata[Ram]),
.rvalid_o (device_rvalid[Ram]),
.rdata_o (device_rdata[Ram])
.clk_i (clk_sys ),
.rst_ni (rst_sys_n ),
.req_i (device_req[Ram] ),
.we_i (device_we[Ram] ),
.be_i (device_be[Ram] ),
.addr_i (device_addr[Ram] ),
.wdata_i (device_wdata[Ram] ),
.rvalid_o (device_rvalid[Ram]),
.rdata_o (device_rdata[Ram] )
);

// RISC-V test utility, used by the RISC-V compliance test to interact with
// the simulator.
riscv_testutil
u_riscv_testutil(
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
.clk_i (clk_sys ),
.rst_ni (rst_sys_n ),

// Device port
.dev_req_i (device_req[TestUtilDevice]),
.dev_we_i (device_we[TestUtilDevice]),
.dev_addr_i (device_addr[TestUtilDevice]),
.dev_wdata_i (device_wdata[TestUtilDevice]),
.dev_req_i (device_req[TestUtilDevice] ),
.dev_we_i (device_we[TestUtilDevice] ),
.dev_addr_i (device_addr[TestUtilDevice] ),
.dev_wdata_i (device_wdata[TestUtilDevice] ),
.dev_rvalid_o (device_rvalid[TestUtilDevice]),
.dev_rdata_o (device_rdata[TestUtilDevice]),
.dev_be_i (device_be[TestUtilDevice]),
.dev_err_o (device_err[TestUtilDevice]),
.dev_rdata_o (device_rdata[TestUtilDevice] ),
.dev_be_i (device_be[TestUtilDevice] ),
.dev_err_o (device_err[TestUtilDevice] ),

// Host port
.host_req_o (host_req[TestUtilHost]),
.host_gnt_i (host_gnt[TestUtilHost]),
.host_rvalid_i (host_rvalid[TestUtilHost]),
.host_addr_o (host_addr[TestUtilHost]),
.host_rdata_i (host_rdata[TestUtilHost])
.host_req_o (host_req[TestUtilHost] ),
.host_gnt_i (host_gnt[TestUtilHost] ),
.host_rvalid_i (host_rvalid[TestUtilHost] ),
.host_addr_o (host_addr[TestUtilHost] ),
.host_rdata_i (host_rdata[TestUtilHost] )
);

endmodule
39 changes: 33 additions & 6 deletions examples/simple_system/ibex_simple_system.core
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,36 +27,60 @@ parameters:
datatype: int
paramtype: vlogparam
default: 1
description: Enable the M ISA extension (hardware multiply/divide) [0/1]
description: "Enable the M ISA extension (hardware multiply/divide) [0/1]"

RV32E:
datatype: int
paramtype: vlogparam
default: 0
description: Enable the E ISA extension (reduced register set) [0/1]
description: "Enable the E ISA extension (reduced register set) [0/1]"

RV32B:
datatype: int
paramtype: vlogparam
default: 0
description: Enable the B ISA extension (bit manipulation EXPERIMENTAL) [0/1]
description: "Enable the B ISA extension (bit manipulation EXPERIMENTAL) [0/1]"

SRAM_INIT_FILE:
datatype: str
paramtype: vlogdefine
description: Path to a vmem file to initialize the RAM with
description: "Path to a vmem file to initialize the RAM with"

MultiplierImplementation:
datatype: str
paramtype: vlogparam
description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
default: "fast"

BranchTargetALU:
datatype: int
paramtype: vlogparam
default: 0
description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)"

WritebackStage:
datatype: int
paramtype: vlogparam
default: 0
description: Enables third pipeline stage (EXPERIMENTAL)
description: "Enables third pipeline stage (EXPERIMENTAL)"

PMPEnable:
datatype: int
default: 0
paramtype: vlogparam
description: "Enable PMP"

PMPGranularity:
datatype: int
default: 0
paramtype: vlogparam
description: "Granularity of NAPOT range, 0 = 4 byte, 1 = byte, 2 = 16 byte, 3 = 32 byte etc"

PMPNumRegions:
datatype: int
default: 0
paramtype: vlogparam
description: "Number of PMP regions"

targets:
sim:
Expand All @@ -71,6 +95,9 @@ targets:
- MultiplierImplementation
- BranchTargetALU
- WritebackStage
- PMPEnable
- PMPGranularity
- PMPNumRegions
- SRAM_INIT_FILE
toplevel: ibex_simple_system
tools:
Expand Down
12 changes: 9 additions & 3 deletions examples/simple_system/rtl/ibex_simple_system.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,9 @@ module ibex_simple_system (
input IO_RST_N
);

parameter bit PMPEnable = 1'b0;
parameter int unsigned PMPGranularity = 0;
parameter int unsigned PMPNumRegions = 4;
parameter bit RV32E = 1'b0;
parameter bit RV32M = 1'b1;
parameter bit RV32B = 1'b0;
Expand Down Expand Up @@ -138,15 +141,18 @@ module ibex_simple_system (
);

ibex_core_tracing #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.MHPMCounterNum ( 29 ),
.DmHaltAddr ( 32'h00100000 ),
.DmExceptionAddr ( 32'h00100000 ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
.WritebackStage ( WritebackStage ),
.MultiplierImplementation ( MultiplierImplementation )
.MultiplierImplementation ( MultiplierImplementation ),
.DmHaltAddr ( 32'h00100000 ),
.DmExceptionAddr ( 32'h00100000 )
) u_core (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
Expand Down
Loading

0 comments on commit 00b46d9

Please sign in to comment.