Update .core files to add full parameter support

- Switch to boolean parameters where this makes sense
- Add MultiplierImplementation

dv/riscv_compliance/ibex_riscv_compliance.core

@@ -25,25 +25,30 @@ filesets:
 
 parameters:
   RV32M:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 1
-    description: Enable the M ISA extension (hardware multiply/divide) [0/1]
+    default: true
+    description: Enable the M ISA extension (hardware multiply/divide)
   RV32E:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: Enable the E ISA extension (reduced register set) [0/1]
+    default: false
+    description: Enable the E ISA extension (reduced register set)
+  MultiplierImplementation:
+    datatype: str
+    paramtype: vlogparam
+    description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
+    default: "fast"
   BranchTargetALU:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]
+    default: false
+    description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
   WritebackStage:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: Enables third pipeline stage (EXPERIMENTAL) [0/1]
+    default: false
+    description: Enables third pipeline stage (EXPERIMENTAL)
 
 targets:
   sim:
@@ -54,6 +59,7 @@ targets:
     parameters:
       - RV32M
       - RV32E
+      - MultiplierImplementation
       - BranchTargetALU
       - WritebackStage
     toplevel: ibex_riscv_compliance

dv/riscv_compliance/rtl/ibex_riscv_compliance.sv

@@ -15,10 +15,11 @@ module ibex_riscv_compliance (
   input IO_RST_N
 );
 
-  parameter bit RV32E           = 1'b0;
-  parameter bit RV32M           = 1'b1;
-  parameter bit BranchTargetALU = 1'b0;
-  parameter bit WritebackStage  = 1'b0;
+  parameter bit RV32E                    = 1'b0;
+  parameter bit RV32M                    = 1'b1;
+  parameter     MultiplierImplementation = "fast";
+  parameter bit BranchTargetALU          = 1'b0;
+  parameter bit WritebackStage           = 1'b0;
 
   logic clk_sys, rst_sys_n;
 
@@ -107,6 +108,7 @@ module ibex_riscv_compliance (
       .DmExceptionAddr(32'h00000000),
       .RV32E(RV32E),
       .RV32M(RV32M),
+      .MultiplierImplementation(MultiplierImplementation),
       .BranchTargetALU(BranchTargetALU),
       .WritebackStage(WritebackStage)
     ) u_core (

examples/simple_system/ibex_simple_system.core

@@ -24,29 +24,34 @@ filesets:
 
 parameters:
   RV32M:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 1
+    default: true
     description: Enable the M ISA extension (hardware multiply/divide) [0/1]
   RV32E:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
+    default: false
     description: Enable the E ISA extension (reduced register set) [0/1]
   SRAM_INIT_FILE:
     datatype: str
     paramtype: vlogdefine
     description: Path to a vmem file to initialize the RAM with
+  MultiplierImplementation:
+    datatype: str
+    paramtype: vlogparam
+    description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
+    default: "fast"
   BranchTargetALU:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]
+    default: false
+    description: Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)
   WritebackStage:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: Enables third pipeline stage (EXPERIMENTAL) [0/1]
+    default: false
+    description: Enables third pipeline stage (EXPERIMENTAL)
 
 targets:
   sim:
@@ -57,6 +62,7 @@ targets:
     parameters:
       - RV32M
       - RV32E
+      - MultiplierImplementation
       - BranchTargetALU
       - WritebackStage
       - SRAM_INIT_FILE

examples/simple_system/rtl/ibex_simple_system.sv

@@ -19,10 +19,11 @@ module ibex_simple_system (
   input IO_RST_N
 );
 
-  parameter bit RV32E           = 1'b0;
-  parameter bit RV32M           = 1'b1;
-  parameter bit BranchTargetALU = 1'b0;
-  parameter bit WritebackStage  = 1'b0;
+  parameter bit RV32E                    = 1'b0;
+  parameter bit RV32M                    = 1'b1;
+  parameter bit BranchTargetALU          = 1'b0;
+  parameter bit WritebackStage           = 1'b0;
+  parameter     MultiplierImplementation = "fast";
 
   logic clk_sys = 1'b0, rst_sys_n;
 
@@ -104,10 +105,10 @@ module ibex_simple_system (
   assign device_err[SimCtrl] = 1'b0;
 
   bus #(
-    .NrDevices   (NrDevices),
-    .NrHosts     (NrHosts  ),
-    .DataWidth   (32       ),
-    .AddressWidth(32       )
+    .NrDevices    ( NrDevices ),
+    .NrHosts      ( NrHosts   ),
+    .DataWidth    ( 32        ),
+    .AddressWidth ( 32        )
   ) u_bus (
     .clk_i               (clk_sys),
     .rst_ni              (rst_sys_n),
@@ -136,13 +137,14 @@ module ibex_simple_system (
   );
 
   ibex_core_tracing #(
-      .MHPMCounterNum(29),
-      .DmHaltAddr(32'h00100000),
-      .DmExceptionAddr(32'h00100000),
-      .RV32E(RV32E),
-      .RV32M(RV32M),
-      .BranchTargetALU(BranchTargetALU),
-      .WritebackStage(WritebackStage)
+      .MHPMCounterNum           ( 29                       ),
+      .DmHaltAddr               ( 32'h00100000             ),
+      .DmExceptionAddr          ( 32'h00100000             ),
+      .RV32E                    ( RV32E                    ),
+      .RV32M                    ( RV32M                    ),
+      .BranchTargetALU          ( BranchTargetALU          ),
+      .WritebackStage           ( WritebackStage           ),
+      .MultiplierImplementation ( MultiplierImplementation )
     ) u_core (
       .clk_i                 (clk_sys),
       .rst_ni                (rst_sys_n),

ibex_core.core

@@ -84,16 +84,16 @@ parameters:
     default: false
 
   BranchTargetALU:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
+    default: false
+    description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL)"
 
   WritebackStage:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
-    description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
+    default: false
+    description: "Enables third pipeline stage (EXPERIMENTAL)"
 
 targets:
   default:

ibex_core_tracing.core

@@ -34,17 +34,19 @@ parameters:
 
   RV32E:
     datatype: bool
+    default: false
     paramtype: vlogparam
 
   RV32M:
     datatype: bool
+    default: true
     paramtype: vlogparam
 
   MultiplierImplementation:
     datatype: str
     paramtype: vlogparam
-    description: "Multiplier implementation. Valid values: fast, slow"
-    default: fast
+    description: "Multiplier implementation. Valid values: fast, slow, single-cycle"
+    default: "fast"
 
   ICache:
     datatype: bool
@@ -59,12 +61,16 @@ parameters:
     default: false
 
   BranchTargetALU:
-    datatype: int
+    datatype: bool
     paramtype: vlogparam
-    default: 0
+    default: false
     description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
 
-
+  WritebackStage:
+    datatype: bool
+    paramtype: vlogparam
+    default: false
+    description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
 
 targets:
   default:
@@ -84,6 +90,11 @@ targets:
     parameters:
       - RVFI=true
       - SYNTHESIS=true
+      - RV32M
+      - RV32E
+      - BranchTargetALU
+      - WritebackStage
+      - MultiplierImplementation
     default_tool: verilator
     toplevel: ibex_core_tracing
     tools: