[dv] Remove clock gating primitive in dv/uvm/tb

This commit removes a copy of the dummy clock gating primitive from tree previously used for UVM-based DV. There is another, identical copy of the same primitive in `shared/rtl` that can be used instead. This resolves lowRISC#213. Signed-off-by: Pirmin Vogel <[email protected]>
mundaym · Nov 15, 2019 · 40d6368 · 40d6368
1 parent aefbcdc
commit 40d6368
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Showing 5 changed files with 6 additions and 32 deletions.
diff --git a/dv/uvm/ibex_dv.f b/dv/uvm/ibex_dv.f
@@ -6,7 +6,7 @@
 +define+TRACE_EXECUTION
 +define+RVFI
 
-${PRJ_DIR}/ibex/dv/uvm/tb/prim_clock_gating.sv
+${PRJ_DIR}/ibex/shared/rtl/prim_clock_gating.sv
 
 // ibex CORE RTL files
 +incdir+${PRJ_DIR}/ibex/rtl

diff --git a/dv/uvm/tb/prim_clock_gating.sv b/dv/uvm/tb/prim_clock_gating.sv
diff --git a/ibex_core.core b/ibex_core.core
@@ -30,8 +30,8 @@ filesets:
     file_type: systemVerilogSource
 
   files_lint:
-    files:
-      - dv/uvm/tb/prim_clock_gating.sv: {file_type: systemVerilogSource}
+    depend:
+      - lowrisc:ibex:sim_shared
 
   files_lint_verilator:
     files:

diff --git a/ibex_core_tracing.core b/ibex_core_tracing.core
@@ -14,8 +14,8 @@ filesets:
     file_type: systemVerilogSource
 
   files_lint:
-    files:
-      - dv/uvm/tb/prim_clock_gating.sv: {file_type: systemVerilogSource}
+    depend:
+      - lowrisc:ibex:sim_shared
 
   files_lint_verilator:
     files:

diff --git a/shared/rtl/prim_clock_gating.sv b/shared/rtl/prim_clock_gating.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
-// Dummy clock gating module
+// Dummy clock gating module compatible with latch-based register file
 
 module prim_clock_gating (
     input        clk_i,