Fix and waive Verilator lint errors in tb_cs_registers

Add a waiver for top-level parameters passed in through the command
line, and fix the use within the file.

dv/cs_registers/lint/verilator_waiver.vlt

@@ -0,0 +1,32 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Lint waivers for processing simple_system RTL with Verilator
+//
+// This should be used for rules applying to things like testbench
+// top-levels. For rules that apply to the actual design (files in the
+// 'rtl' directory), see verilator_waiver_rtl.vlt in the same
+// directory.
+//
+// See https://www.veripool.org/projects/verilator/wiki/Manual-verilator#CONFIGURATION-FILES
+// for documentation.
+//
+// Important: This file must included *before* any other Verilog file is read.
+// Otherwise, only global waivers are applied, but not file-specific waivers.
+
+`verilator_config
+
+// We use boolean top-level parameters.
+// When building with fusesoc, these get set with defines like
+// -GRV32M=1 (rather than -GRV32M=1'b1), leading to warnings like:
+//
+//   Operator VAR '<varname>' expects 1 bits on the Initial value, but
+//   Initial value's CONST '32'h1' generates 32 bits.
+//
+// This signoff rule ignores errors like this. Note that it only
+// matches when you set a 1-bit value to a literal 1, so it won't hide
+// silly mistakes like setting it to 2.
+//
+lint_off -rule WIDTH -file "*/tb/tb_cs_registers.sv"
+         -match "*expects 1 bits*Initial value's CONST '32'h1'*"

dv/cs_registers/tb/tb_cs_registers.sv

@@ -3,15 +3,15 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module tb_cs_registers #(
-    parameter bit          DbgTriggerEn     = 0,
-    parameter bit          ICache           = 0,
+    parameter bit          DbgTriggerEn     = 1'b0,
+    parameter bit          ICache           = 1'b0,
     parameter int unsigned MHPMCounterNum   = 8,
     parameter int unsigned MHPMCounterWidth = 40,
-    parameter bit          PMPEnable        = 0,
+    parameter bit          PMPEnable        = 1'b0,
     parameter int unsigned PMPGranularity   = 0,
     parameter int unsigned PMPNumRegions    = 4,
-    parameter bit          RV32E            = 0,
-    parameter bit          RV32M            = 0
+    parameter bit          RV32E            = 1'b0,
+    parameter bit          RV32M            = 1'b0
 ) (
     // Clock and Reset
     inout  wire                 clk_i,

dv/cs_registers/tb_cs_registers.core

@@ -30,11 +30,12 @@ filesets:
       - model/register_model.h
     file_type: user
 
-  files_sim_verilator:
+  files_verilator:
     depend:
       - lowrisc:dv_verilator:simutil_verilator
     files:
       - tb/tb_cs_registers.cc: { file_type: cppSource }
+      - lint/verilator_waiver.vlt: {file_type: vlt}
 
   files_sim:
     depend:
@@ -90,7 +91,7 @@ targets:
     toplevel: tb_cs_registers
     filesets:
       - files_sim
-      - files_sim_verilator
+      - tool_verilator ? (files_verilator)
     hooks:
       pre_build:
         - build_so