Fix RegFile parameter overriding in ArtyA7 example

Signed-off-by: Pirmin Vogel <[email protected]>
mundaym · Aug 21, 2020 · 9eebf52 · 9eebf52
1 parent 62109d4
commit 9eebf52
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv
@@ -43,7 +43,7 @@ module top_artya7 (
 
 
   ibex_core #(
-     .RegFile(RegFileFPGA),
+     .RegFile(ibex_pkg::RegFileFPGA),
      .DmHaltAddr(32'h00000000),
      .DmExceptionAddr(32'h00000000)
   ) u_core (