Remove duplicated files from dv/uvm/core_ibex/common/utils

We now have a clock/reset interface and the dv_utils stuff vendored from OpenTitan so can delete the duplicates and point the file list at the vendored files. The only difficulty is that the clock interfaces are slightly different, so there are a couple of minor changes to the core_ibex test lib, renaming "clk_if" to "clk_rst_if" and changing how we apply resets. Note that the testbench (core_ibex_tb_top.sv) starts the clock and resets the DUT at the start of time. This is different from how other OpenTitan VIP does things (where the reset happens in the sequence), but this is the smallest change I could make from how it worked before (where the reset happened in the clock interface itself).
mundaym · Jul 22, 2020 · e8d86ec · e8d86ec
1 parent 1dda640
commit e8d86ec
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Showing 8 changed files with 19 additions and 316 deletions.
diff --git a/dv/uvm/core_ibex/common/utils/clk_if.sv b/dv/uvm/core_ibex/common/utils/clk_if.sv
diff --git a/dv/uvm/core_ibex/common/utils/dv_macros.svh b/dv/uvm/core_ibex/common/utils/dv_macros.svh
diff --git a/dv/uvm/core_ibex/common/utils/dv_utils_pkg.sv b/dv/uvm/core_ibex/common/utils/dv_utils_pkg.sv
diff --git a/dv/uvm/core_ibex/ibex_dv.f b/dv/uvm/core_ibex/ibex_dv.f
@@ -62,9 +62,11 @@
 +incdir+${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent
 +incdir+${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/irq_agent
 +incdir+${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/mem_model
-+incdir+${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/utils
-${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/utils/clk_if.sv
-${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/utils/dv_utils_pkg.sv
++incdir+${PRJ_DIR}/ibex/vendor/lowrisc_ip/dv_utils
+${PRJ_DIR}/ibex/dv/uvm/top_pkg/top_pkg.sv
+${PRJ_DIR}/ibex/vendor/lowrisc_ip/common_ifs/clk_rst_if.sv
+${PRJ_DIR}/ibex/vendor/lowrisc_ip/common_ifs/pins_if.sv
+${PRJ_DIR}/ibex/vendor/lowrisc_ip/dv_utils/dv_utils_pkg.sv
 ${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/mem_model/mem_model_pkg.sv
 ${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf.sv
 ${PRJ_DIR}/ibex/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv

diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
@@ -11,7 +11,7 @@ module core_ibex_tb_top;
   wire rst_n;
   logic fetch_enable;
 
-  clk_if         ibex_clk_if(.clk(clk), .rst_n(rst_n));
+  clk_rst_if     ibex_clk_if(.clk(clk), .rst_n(rst_n));
   irq_if         irq_vif(.clk(clk));
   ibex_mem_intf  data_mem_vif(.clk(clk));
   ibex_mem_intf  instr_mem_vif(.clk(clk));
@@ -150,7 +150,14 @@ module core_ibex_tb_top;
   assign csr_if.csr_op                        = dut.u_ibex_core.csr_op;
 
   initial begin
-    uvm_config_db#(virtual clk_if)::set(null, "*", "clk_if", ibex_clk_if);
+    // Drive the clock and reset lines. Reset everything and start the clock at the beginning of
+    // time
+    ibex_clk_if.set_active();
+    fork
+      ibex_clk_if.apply_reset(.reset_width_clks (100));
+    join_none
+
+    uvm_config_db#(virtual clk_rst_if)::set(null, "*", "clk_if", ibex_clk_if);
     uvm_config_db#(virtual core_ibex_dut_probe_if)::set(null, "*", "dut_if", dut_if);
     uvm_config_db#(virtual core_ibex_instr_monitor_if)::set(null,
                                                             "*",

diff --git a/dv/uvm/core_ibex/tests/core_ibex_base_test.sv b/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
@@ -6,7 +6,7 @@ class core_ibex_base_test extends uvm_test;
 
   core_ibex_env                                   env;
   core_ibex_env_cfg                               cfg;
-  virtual clk_if                                  clk_vif;
+  virtual clk_rst_if                              clk_vif;
   virtual core_ibex_dut_probe_if                  dut_vif;
   virtual core_ibex_instr_monitor_if              instr_vif;
   virtual core_ibex_csr_if                        csr_vif;
@@ -39,7 +39,7 @@ class core_ibex_base_test extends uvm_test;
   virtual function void build_phase(uvm_phase phase);
     super.build_phase(phase);
     $value$plusargs("timeout_in_cycles=%0d", timeout_in_cycles);
-    if (!uvm_config_db#(virtual clk_if)::get(null, "", "clk_if", clk_vif)) begin
+    if (!uvm_config_db#(virtual clk_rst_if)::get(null, "", "clk_if", clk_vif)) begin
       `uvm_fatal(`gfn, "Cannot get clk_if")
     end
     if (!uvm_config_db#(virtual core_ibex_dut_probe_if)::get(null, "", "dut_if", dut_vif)) begin

diff --git a/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv
@@ -11,7 +11,7 @@ class core_base_seq #(type REQ = uvm_sequence_item) extends uvm_sequence#(REQ);
   int unsigned       iteration_cnt;
   int unsigned       max_interval;
   int unsigned       max_delay = 500;
-  virtual clk_if     clk_vif;
+  virtual clk_rst_if clk_vif;
   bit                is_started;
   bit                stop_seq;
   bit                seq_finished;
@@ -31,7 +31,7 @@ class core_base_seq #(type REQ = uvm_sequence_item) extends uvm_sequence#(REQ);
   }
 
   virtual task body();
-    if(!uvm_config_db#(virtual clk_if)::get(null, "", "clk_if", clk_vif)) begin
+    if(!uvm_config_db#(virtual clk_rst_if)::get(null, "", "clk_if", clk_vif)) begin
        `uvm_fatal(get_full_name(), "Cannot get clk_if")
     end
     `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay)

diff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
@@ -48,7 +48,7 @@ class core_ibex_reset_test extends core_ibex_base_test;
       fork
         begin
           dut_vif.dut_cb.fetch_enable <= 1'b0;
-          clk_vif.reset();
+          clk_vif.apply_reset(.reset_width_clks (100));
         end
         begin
           clk_vif.wait_clks(1);