Update lec_sv2v.sh

mundaym · Jun 20, 2020 · f9badaf · f9badaf
1 parent 31d7971
commit f9badaf
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/syn/lec_sv2v.sh b/syn/lec_sv2v.sh
@@ -57,7 +57,7 @@ cp ../rtl/prim_clock_gating.v .
 cp ../rtl/prim_clock_gating.v prim_clock_gating.sv
 
 #-------------------------------------------------------------------------
-# run LEC (generarted Verilog vs. original SystemVerilog)
+# run LEC (generated Verilog vs. original SystemVerilog)
 #-------------------------------------------------------------------------
 printf "\n\nLEC RESULTS:\n"