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Commits on Jul 7, 2020

• Only include necessary LFSR primitive

  Show description for c476329
  imphil

  committed
  c476329

• Update lowrisc_ip to lowRISC/opentitan@ebf4663b

  Show description for ee0a1cf
  imphil

  committed
  ee0a1cf

• [dv/ibex] Add two new interrupt/debug tests

  Show description for 75dadb5
  

  Udi

  authored and

  sriyerg

  committed
  75dadb5

Commits on Jul 6, 2020

• [doc] Fix spelling of CoreMark

  Show description for 414ff7e
  vogelpi

  committed
  414ff7e

• Handle --help properly in simple_system top-level

  rswarbrick

  committed
  d7284c2

• Update lowrisc_ip to lowRISC/opentitan@9ac4f9c8

  Show description for 45d3790
  rswarbrick

  committed
  45d3790

• Use the Xilinx primitives for the Arty board

  Show description for f98ddab
  imphil

  committed
  f98ddab

Commits on Jul 5, 2020

• [doc] Clarify that the supported version of the B extension is a draft

  Show description for ede658b
  vogelpi

  committed
  ede658b

Commits on Jul 3, 2020

• Clean up Verilator sections in core files

  Show description for 0335b69
  imphil

  committed
  0335b69

• Fix and waive Verilator lint errors in tb_cs_registers

  Show description for 9e3bec0
  imphil

  committed
  9e3bec0

• Remove lowrisc:prim:clock_gating from shared core collections

  Show description for 9bd09c0
  imphil

  committed
  9bd09c0

• Add lint for ibex_simple_system to CI

  imphil

  committed
  465ea28

• ibex_simple_system: Add lint target

  imphil

  committed
  a10df87

• Simplify lint targets

  Show description for 3bc1054
  imphil

  committed
  3bc1054

• Remove unrelated files from lint in ibex_core_tracing

  Show description for c436ea1
  imphil

  committed
  c436ea1

• Add dependency on prim_clock_gating

  Show description for 89e525e
  imphil

  committed
  89e525e

• Fix Ibex description in core file

  Show description for a126e4c
  imphil

  committed
  a126e4c

• icache: Depend on prim_assert

  Show description for dbc1f25
  imphil

  committed
  dbc1f25

• Fix SRAM initialisation for fpga/artya example

  Show description for 006617f
  rswarbrick

  committed
  006617f

• Drop SRAM_INIT_FILE from ibex_riscv_compliance.core

  Show description for 7b6ba11
  rswarbrick

  committed
  7b6ba11

• Get simple_system working for VCS

  Show description for a8cc0a9
  rswarbrick

  committed
  a8cc0a9

• Pass MemInitFile parameter from our ram_*p wrappers

  Show description for 8e9a621
  rswarbrick

  committed
  8e9a621

• Update lowrisc_ip to lowRISC/opentitan@976d9b9c

  Show description for 711505a
  imphil

  committed
  711505a

• Icache: It's not a draft any more

  Show description for bf5dd7e
  imphil

  committed
  bf5dd7e

• Remove outdated documentation

  Show description for 6ca325f
  imphil

  committed
  6ca325f

• CI: Show exact command to run Verilator lint

  Show description for b807879
  imphil

  committed
  b807879

• CI: Enable Verible lint for all configs

  imphil

  committed
  18db64f

• CI: use the new binary name of Verible

  Show description for df634b9
  imphil

  committed
  df634b9

• Add a waiver file for Verible lint

  Show description for 4ee8b24
  imphil

  committed
  4ee8b24

• Fix Verible lint issues

  Show description for 67e7417
  imphil

  committed
  67e7417

Commits on Jul 2, 2020

• Add some formal cover properties for ICache

  Show description for fb2a17a
  rswarbrick

  committed
  fb2a17a

• Add an ICacheECC parameter to ICache formal flow

  Show description for 4a20bc4
  rswarbrick

  committed
  4a20bc4

• Formal protocol checking for icache <-> core interface

  Show description for 49c9113
  rswarbrick

  committed
  49c9113

• A simple formal flow for the ICache based on SymbiYosys

  Show description for ee1ca61
  rswarbrick

  committed
  ee1ca61

• Move riscv-formal code into formal/riscv-formal

  Show description for e4dbe46
  rswarbrick

  committed
  e4dbe46

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