Add menvcfg.PBMTE / henvcfg.PBMTE

Architecture Review of the Svpbmt extension concluded that adding a
mechanism to disable availability of Svpbmt was desirable, because
(for example) if a hypervisor can know with certainty that its guest
cannot modify the memory attributes, then it can avoid cache flushing
in certain device-emulation regimes.

Priv specs are ratified

Add VS field

This was already ratified as part of the V extension.

Clarify that implicit reads of CSRs return same value as explicit rea…

…ds (riscv#783)

Seems like the kind of thing that could've gone without saying, but it has
come up in conversation a number of times---including wrt. the recent
CSR Field Modulation discussion in riscv#782.

So, make it crystal clear.

Add VS field

This was already ratified as part of the V extension.

Fix typo

Remark that Svnapot and Svpbmt require Sv39

Resolves riscv#785

Add Hazard3 to open-source marchid list (riscv#784)

This is a 3-stage `RV32I` core, with optional support for `M`/`C`/`Zba`/`Zbb`/`Zbc`/`Zbs` and debug support. It passes the ISA compliance tests, riscv-formal, OpenOCD DM compliance tests and the end-to-end debug tests from riscv-tests/debug.

[Github](https://github.com/Wren6991/Hazard3/blob/master/License)

[PDF documentation](https://github.com/Wren6991/Hazard3/blob/master/doc/hazard3.pdf)

The license is DWTFPLv3, which is effectively a public domain dedication.

Merge branch 'jhauser-us-jhauser-2021-CSRFieldMods'

Fix typo