Merge pull request capstone-engine#2096 from peace-maker/python_sh

Add Python bindings for SH

.gitignore

@@ -72,6 +72,7 @@ tests/test_evm
 tests/test_wasm
 tests/test_mos65xx
 tests/test_bpf
+tests/test_sh
 tests/test_riscv
 
 # regress binaries

bindings/const_generator.py

@@ -5,7 +5,7 @@
 
 INCL_DIR = '../include/capstone/'
 
-include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'tricore.h' ]
+include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ]
 
 template = {
     'java': {
@@ -53,6 +53,7 @@
             'mos65xx.h': 'mos65xx',
             'bpf.h': 'bpf',
             'riscv.h': 'riscv',
+            'sh.h': 'sh',
             'tricore.h': ['TRICORE', 'TriCore'],
             'comment_open': '#',
             'comment_close': '',

bindings/python/capstone/__init__.py

@@ -35,10 +35,11 @@
     'CS_ARCH_TMS320C64X',
     'CS_ARCH_M680X',
     'CS_ARCH_EVM',
+    'CS_ARCH_MOS65XX',
     'CS_ARCH_WASM',
     'CS_ARCH_BPF',
     'CS_ARCH_RISCV',
-    'CS_ARCH_MOS65XX',
+    'CS_ARCH_SH',
     'CS_ARCH_TRICORE',
     'CS_ARCH_ALL',
 
@@ -90,6 +91,13 @@
     'CS_MODE_MOS65XX_65816_LONG_M',
     'CS_MODE_MOS65XX_65816_LONG_X',
     'CS_MODE_MOS65XX_65816_LONG_MX',
+    'CS_MODE_SH2',
+    'CS_MODE_SH2A',
+    'CS_MODE_SH3',
+    'CS_MODE_SH4',
+    'CS_MODE_SH4A',
+    'CS_MODE_SHFPU',
+    'CS_MODE_SHDSP',
     'CS_MODE_TRICORE_110',
     'CS_MODE_TRICORE_120',
     'CS_MODE_TRICORE_130',
@@ -207,7 +215,7 @@
 CS_ARCH_WASM = 13
 CS_ARCH_BPF = 14
 CS_ARCH_RISCV = 15
-# CS_ARCH_SH = 16
+CS_ARCH_SH = 16
 CS_ARCH_TRICORE = 17
 CS_ARCH_MAX = 18
 CS_ARCH_ALL = 0xFFFF
@@ -261,6 +269,13 @@
 CS_MODE_MOS65XX_65816_LONG_M = (1 << 5) # MOS65XXX WDC 65816, 16-bit m, 8-bit x 
 CS_MODE_MOS65XX_65816_LONG_X = (1 << 6) # MOS65XXX WDC 65816, 8-bit m, 16-bit x
 CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X
+CS_MODE_SH2 = 1 << 1   # SH2
+CS_MODE_SH2A = 1 << 2  # SH2A
+CS_MODE_SH3 = 1 << 3   # SH3
+CS_MODE_SH4 = 1 << 4   # SH4
+CS_MODE_SH4A = 1 << 5  # SH4A
+CS_MODE_SHFPU = 1 << 6 # w/ FPU
+CS_MODE_SHDSP = 1 << 7 # w/ DSP
 CS_MODE_TRICORE_110 = 1 << 1 # Tricore 1.1
 CS_MODE_TRICORE_120 = 1 << 2 # Tricore 1.2
 CS_MODE_TRICORE_130 = 1 << 3 # Tricore 1.3
@@ -425,7 +440,7 @@ def copy_ctypes_list(src):
     return [copy_ctypes(n) for n in src]
 
 # Weird import placement because these modules are needed by the below code but need the above functions
-from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, tricore
+from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore
 
 class _cs_arch(ctypes.Union):
     _fields_ = (
@@ -445,6 +460,7 @@ class _cs_arch(ctypes.Union):
         ('wasm', wasm.CsWasm),
         ('bpf', bpf.CsBPF),
         ('riscv', riscv.CsRISCV),
+        ('sh', sh.CsSH),
         ('tricore', tricore.CsTriCore),
     )
 
@@ -772,6 +788,8 @@ def __gen_detail(self):
             (self.operands) = bpf.get_arch_info(self._raw.detail.contents.arch.bpf)
         elif arch == CS_ARCH_RISCV:
             (self.need_effective_addr, self.operands) = riscv.get_arch_info(self._raw.detail.contents.arch.riscv)
+        elif arch == CS_ARCH_SH:
+            (self.sh_insn, self.sh_size, self.operands) = sh.get_arch_info(self._raw.detail.contents.arch.sh)
         elif arch == CS_ARCH_TRICORE:
             (self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore)
 
@@ -1240,7 +1258,7 @@ def debug():
         "sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X,
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
         'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
-        'wasm': CS_ARCH_WASM,
+        'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH,
     }
 
     all_archs = ""

bindings/python/capstone/sh.py

@@ -0,0 +1,66 @@
+# Capstone Python bindings, by Peace-Maker <[email protected]>
+
+import ctypes
+from . import copy_ctypes_list
+from .sh_const import *
+
+# define the API
+class SHOpMem(ctypes.Structure):
+    _fields_ = (
+        ('address', ctypes.c_uint),
+        ('reg', ctypes.c_uint),
+        ('disp', ctypes.c_uint32),
+    )
+
+class SHOpDsp(ctypes.Structure):
+    _fields_ = (
+        ('insn', ctypes.c_uint),
+        ('operand', ctypes.c_uint * 2),
+        ('r', ctypes.c_uint * 6),
+        ('cc', ctypes.c_uint),
+        ('imm', ctypes.c_uint8),
+        ('size', ctypes.c_int),
+    )
+
+class SHOpValue(ctypes.Union):
+    _fields_ = (
+        ('imm', ctypes.c_int64),
+        ('reg', ctypes.c_uint),
+        ('mem', SHOpMem),
+        ('dsp', SHOpDsp),
+    )
+
+class SHOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', SHOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+    @property
+    def dsp(self):
+        return self.value.dsp
+
+
+class CsSH(ctypes.Structure):
+    _fields_ = (
+        ('insn', ctypes.c_uint),
+        ('size', ctypes.c_uint8),
+        ('op_count', ctypes.c_uint8),
+        ('operands', SHOp * 3),
+    )
+
+def get_arch_info(a):
+    return (a.insn, a.size, copy_ctypes_list(a.operands[:a.op_count]))
+