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[ARM] Split A/R class into separate subtarget features.
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Patch by Bradley Smith.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
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@aemerson
aemerson committed Sep 23, 2013
1 parent baca533 commit 0f22c13
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Showing 5 changed files with 37 additions and 23 deletions.
31 changes: 21 additions & 10 deletions lib/Target/ARM/ARM.td
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Original file line number Diff line number Diff line change
Expand Up @@ -117,10 +117,18 @@ def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
"Supports Multiprocessing extension">;

// M-series ISA?
def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
// M-series ISA
def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
"Is microcontroller profile ('M' series)">;

// R-series ISA
def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
"Is realtime profile ('R' series)">;

// A-series ISA
def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
"Is application profile ('A' series)">;

// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
// See ARMInstrInfo.td for details.
def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
Expand Down Expand Up @@ -261,26 +269,29 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
def : ProcessorModel<"cortex-a5", CortexA8Model,
[ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
FeatureVFP4, FeatureDSPThumb2,
FeatureHasRAS]>;
FeatureHasRAS, FeatureAClass]>;
def : ProcessorModel<"cortex-a8", CortexA8Model,
[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2, FeatureHasRAS]>;
FeatureDSPThumb2, FeatureHasRAS,
FeatureAClass]>;
def : ProcessorModel<"cortex-a9", CortexA9Model,
[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2, FeatureHasRAS]>;
FeatureDSPThumb2, FeatureHasRAS,
FeatureAClass]>;
def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2, FeatureMP,
FeatureHasRAS]>;
FeatureHasRAS, FeatureAClass]>;
// FIXME: A15 has currently the same ProcessorModel as A9.
def : ProcessorModel<"cortex-a15", CortexA9Model,
[ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2, FeatureHasRAS]>;
FeatureDSPThumb2, FeatureHasRAS,
FeatureAClass]>;
// FIXME: R5 has currently the same ProcessorModel as A8.
def : ProcessorModel<"cortex-r5", CortexA8Model,
[ProcR5, HasV7Ops, FeatureDB,
FeatureVFP3, FeatureDSPThumb2,
FeatureHasRAS]>;
FeatureHasRAS, FeatureRClass]>;

// V7M Processors.
def : ProcNoItin<"cortex-m3", [HasV7Ops,
Expand All @@ -298,10 +309,10 @@ def : ProcNoItin<"cortex-m4", [HasV7Ops,
def : ProcessorModel<"swift", SwiftModel,
[ProcSwift, HasV7Ops, FeatureNEON,
FeatureDB, FeatureDSPThumb2,
FeatureHasRAS]>;
FeatureHasRAS, FeatureAClass]>;

// V8 Processors
def : ProcNoItin<"cortex-a53", [HasV8Ops]>;
def : ProcNoItin<"cortex-a53", [HasV8Ops, FeatureAClass]>;

//===----------------------------------------------------------------------===//
// Register File Description
Expand Down
6 changes: 3 additions & 3 deletions lib/Target/ARM/ARMInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -244,10 +244,10 @@ def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
AssemblerPredicate<"ModeThumb,FeatureThumb2",
"thumb2">;
def IsMClass : Predicate<"Subtarget->isMClass()">,
AssemblerPredicate<"FeatureMClass", "armv7m">;
def IsARClass : Predicate<"!Subtarget->isMClass()">,
AssemblerPredicate<"FeatureMClass", "armv*m">;
def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
AssemblerPredicate<"!FeatureMClass",
"armv7a/r">;
"!armv*m">;
def IsARM : Predicate<"!Subtarget->isThumb()">,
AssemblerPredicate<"!ModeThumb", "arm-mode">;
def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
Expand Down
6 changes: 3 additions & 3 deletions lib/Target/ARM/ARMInstrThumb2.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3922,7 +3922,7 @@ defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
//
// A/R class can only move from CPSR or SPSR.
def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
[]>, Requires<[IsThumb2,IsARClass]> {
[]>, Requires<[IsThumb2,IsNotMClass]> {
bits<4> Rd;
let Inst{31-12} = 0b11110011111011111000;
let Inst{11-8} = Rd;
Expand All @@ -3932,7 +3932,7 @@ def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;

def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
[]>, Requires<[IsThumb2,IsARClass]> {
[]>, Requires<[IsThumb2,IsNotMClass]> {
bits<4> Rd;
let Inst{31-12} = 0b11110011111111111000;
let Inst{11-8} = Rd;
Expand Down Expand Up @@ -3965,7 +3965,7 @@ def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
// the mask with the fields to be accessed in the special register.
def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
NoItinerary, "msr", "\t$mask, $Rn", []>,
Requires<[IsThumb2,IsARClass]> {
Requires<[IsThumb2,IsNotMClass]> {
bits<5> mask;
bits<4> Rn;
let Inst{31-21} = 0b11110011100;
Expand Down
2 changes: 1 addition & 1 deletion lib/Target/ARM/ARMSubtarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, const TargetOptions &Options)
: ARMGenSubtargetInfo(TT, CPU, FS)
, ARMProcFamily(Others)
, ARMProcClass(None)
, stackAlignment(4)
, CPUString(CPU)
, TargetTriple(TT)
Expand Down Expand Up @@ -90,7 +91,6 @@ void ARMSubtarget::initializeEnvironment() {
SlowFPBrcc = false;
InThumbMode = false;
HasThumb2 = false;
IsMClass = false;
NoARM = false;
PostRAScheduler = false;
IsR9Reserved = ReserveR9;
Expand Down
15 changes: 9 additions & 6 deletions lib/Target/ARM/ARMSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,10 +33,16 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass
};

/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcFamilyEnum ARMProcFamily;

/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
ARMProcClassEnum ARMProcClass;

/// HasV4TOps, HasV5TOps, HasV5TEOps,
/// HasV6Ops, HasV6T2Ops, HasV7Ops, HasV8Ops -
/// Specify whether target support specific ARM ISA variants.
Expand Down Expand Up @@ -82,10 +88,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
/// HasThumb2 - True if Thumb2 instructions are supported.
bool HasThumb2;

/// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
/// v6m, v7m for example.
bool IsMClass;

/// NoARM - True if subtarget does not support ARM mode execution.
bool NoARM;

Expand Down Expand Up @@ -300,8 +302,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
bool isThumb2() const { return InThumbMode && HasThumb2; }
bool hasThumb2() const { return HasThumb2; }
bool isMClass() const { return IsMClass; }
bool isARClass() const { return !IsMClass; }
bool isMClass() const { return ARMProcClass == MClass; }
bool isRClass() const { return ARMProcClass == RClass; }
bool isAClass() const { return ARMProcClass == AClass; }

bool isR9Reserved() const { return IsR9Reserved; }

Expand Down

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