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[X86][SSE] Add i686 triple tests for partial vector and re-association
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302149 91177308-0d34-0410-b5e6-96231b3b80d8
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@RKSimon
RKSimon committed May 4, 2017
1 parent 80e222e commit 547297e
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Showing 2 changed files with 135 additions and 61 deletions.
36 changes: 25 additions & 11 deletions test/CodeGen/X86/vec_partial.ll
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@@ -1,32 +1,46 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64

; PR11580
define <3 x float> @addf3(<3 x float> %x) {
; CHECK-LABEL: addf3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
; X86-LABEL: addf3:
; X86: # BB#0: # %entry
; X86-NEXT: addps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: addf3:
; X64: # BB#0: # %entry
; X64-NEXT: addps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
entry:
%add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
ret <3 x float> %add
}

; PR11580
define <4 x float> @cvtf3_f4(<3 x float> %x) {
; CHECK-LABEL: cvtf3_f4:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: retq
; X86-LABEL: cvtf3_f4:
; X86: # BB#0: # %entry
; X86-NEXT: retl
;
; X64-LABEL: cvtf3_f4:
; X64: # BB#0: # %entry
; X64-NEXT: retq
entry:
%extractVec = shufflevector <3 x float> %x, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x float> %extractVec
}

; PR11580
define <3 x float> @cvtf4_f3(<4 x float> %x) {
; CHECK-LABEL: cvtf4_f3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: retq
; X86-LABEL: cvtf4_f3:
; X86: # BB#0: # %entry
; X86-NEXT: retl
;
; X64-LABEL: cvtf4_f3:
; X64: # BB#0: # %entry
; X64-NEXT: retq
entry:
%extractVec = shufflevector <4 x float> %x, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x float> %extractVec
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160 changes: 110 additions & 50 deletions test/CodeGen/X86/vec_reassociate.ll
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@@ -1,117 +1,177 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64

define <4 x i32> @add_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @add_4i32
;CHECK: # BB#0:
;CHECK-NEXT: paddd %xmm1, %xmm0
;CHECK-NEXT: retq
; X86-LABEL: add_4i32:
; X86: # BB#0:
; X86-NEXT: paddd %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: add_4i32:
; X64: # BB#0:
; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: retq
%1 = add <4 x i32> %a0, <i32 1, i32 -2, i32 3, i32 -4>
%2 = add <4 x i32> %a1, <i32 -1, i32 2, i32 -3, i32 4>
%3 = add <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @add_4i32_commute
;CHECK: # BB#0:
;CHECK-NEXT: paddd %xmm1, %xmm0
;CHECK-NEXT: retq
; X86-LABEL: add_4i32_commute:
; X86: # BB#0:
; X86-NEXT: paddd %xmm1, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: add_4i32_commute:
; X64: # BB#0:
; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: retq
%1 = add <4 x i32> <i32 1, i32 -2, i32 3, i32 -4>, %a0
%2 = add <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, %a1
%3 = add <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @mul_4i32
;CHECK: # BB#0:
;CHECK-NEXT: pmulld %xmm1, %xmm0
;CHECK-NEXT: pmulld .LCPI2_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: mul_4i32:
; X86: # BB#0:
; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: pmulld {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: mul_4i32:
; X64: # BB#0:
; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
%3 = mul <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @mul_4i32_commute
;CHECK: # BB#0:
;CHECK-NEXT: pmulld %xmm1, %xmm0
;CHECK-NEXT: pmulld .LCPI3_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: mul_4i32_commute:
; X86: # BB#0:
; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: pmulld {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: mul_4i32_commute:
; X64: # BB#0:
; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
%2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
%3 = mul <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @and_4i32
;CHECK: # BB#0:
;CHECK-NEXT: andps %xmm1, %xmm0
;CHECK-NEXT: andps .LCPI4_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: and_4i32:
; X86: # BB#0:
; X86-NEXT: andps %xmm1, %xmm0
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: and_4i32:
; X64: # BB#0:
; X64-NEXT: andps %xmm1, %xmm0
; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = and <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @and_4i32_commute
;CHECK: # BB#0:
;CHECK-NEXT: andps %xmm1, %xmm0
;CHECK-NEXT: andps .LCPI5_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: and_4i32_commute:
; X86: # BB#0:
; X86-NEXT: andps %xmm1, %xmm0
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: and_4i32_commute:
; X64: # BB#0:
; X64-NEXT: andps %xmm1, %xmm0
; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = and <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @or_4i32
;CHECK: # BB#0:
;CHECK-NEXT: orps %xmm1, %xmm0
;CHECK-NEXT: orps .LCPI6_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: or_4i32:
; X86: # BB#0:
; X86-NEXT: orps %xmm1, %xmm0
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: or_4i32:
; X64: # BB#0:
; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @or_4i32_commute
;CHECK: # BB#0:
;CHECK-NEXT: orps %xmm1, %xmm0
;CHECK-NEXT: orps .LCPI7_0(%rip), %xmm0
;CHECK-NEXT: retq
%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
; X86-LABEL: or_4i32_commute:
; X86: # BB#0:
; X86-NEXT: orps %xmm1, %xmm0
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: or_4i32_commute:
; X64: # BB#0:
; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @xor_4i32
;CHECK: # BB#0:
;CHECK-NEXT: xorps %xmm1, %xmm0
;CHECK-NEXT: xorps .LCPI8_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: xor_4i32:
; X86: # BB#0:
; X86-NEXT: xorps %xmm1, %xmm0
; X86-NEXT: xorps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: xor_4i32:
; X64: # BB#0:
; X64-NEXT: xorps %xmm1, %xmm0
; X64-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = xor <4 x i32> %1, %2
ret <4 x i32> %3
}

define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @xor_4i32_commute
;CHECK: # BB#0:
;CHECK-NEXT: xorps %xmm1, %xmm0
;CHECK-NEXT: xorps .LCPI9_0(%rip), %xmm0
;CHECK-NEXT: retq
; X86-LABEL: xor_4i32_commute:
; X86: # BB#0:
; X86-NEXT: xorps %xmm1, %xmm0
; X86-NEXT: xorps {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: xor_4i32_commute:
; X64: # BB#0:
; X64-NEXT: xorps %xmm1, %xmm0
; X64-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-NEXT: retq
%1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = xor <4 x i32> %1, %2
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