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Commits on May 28, 2017

• [X86] Adding new LLVM TableGen backend that generates the X86 backend memory folding tables.

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  0ccceac

• [X86] Adding FoldGenRegForm helper field (for memory folding tables tableGen backend) to X86Inst class and set its value for the relevant instructions.

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  09d9f45

Commits on May 15, 2017

• [X86] Relocate code of replacement of subtarget unsupported masked memory intrinsics to run also on -O0 option.

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  eadb58f

Commits on May 11, 2017

• [X86] Moving X86Local namespace from .cpp to .h file to use it in memory folding TableGen backend.

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  059f03a

Commits on Apr 26, 2017

• [X86] Add missing mayLoad/mayStore attributes to some X86 instructions (Continue)

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  78f951e

• [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.

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  1ebb1b7

Commits on Apr 23, 2017

• [X86][MPX] Add load & store instructions of bnd values to getLoadStoreRegOpcode function.

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  af17b26

• [X86] Convert test checks to generated checks of update_llc_test_checks.py. NFC

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  e67d6dd

Commits on Apr 13, 2017

• [X86] Added missing mayLoad/mayStore attributes to some X86 instructions.

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  67b5052

• Reverting cmake/modules/AddLLVM.cmake changes from revision 300184 (Added by mistake).

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  4c76a12

• [X86] Change instructions names to keep consistency with the naming convention. NFC

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  456f727

Commits on Mar 7, 2017

• [X86] Quick fix for build bot failure (r297127) due to unused variable.

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  69112bd

• [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables.

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  b59d804

• [X86][AVX512] Add missing entries to EVEX2VEX tables

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  82804ad

Commits on Mar 1, 2017

• [X86] Fix creating vreg def after use.

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  5abd133

Commits on Feb 23, 2017

• [X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.

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  6f30b97

• [X86][AVX512] Remove VCVTSS2SDZ & VCVTSD2SSZ from memory folding tables as they introduce new read dependency when folding.

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  ff35eec

• [X86][AVX512] Change VCVTSS2SD and VCVTSD2SS node types to keep consistency between VEX/EVEX versions.

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  70ad23e

Commits on Feb 22, 2017

• [X86] Fix memory operands definition for some instructions.

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  7f45e91

Commits on Feb 20, 2017

• [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update all AVX instructions with the new value.

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  5cb2278

Commits on Feb 15, 2017

• [X86][AVX] Remove REX_W from AVX instructions.

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  84249f9

Commits on Feb 13, 2017

• [X86][AVX512] Fix operand classes for some AVX512 instructions to keep consistency between VEX/EVEX versions of the same instruction.

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  61207a5

Commits on Jan 4, 2017

• [X86][AVX512] Passing the appropriate memory operand class to INT_{U}COMIS{S|D} instructions

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  99eea60

Commits on Dec 22, 2016

• [X86][AVX2] Passing the appropriate memory operand class to VPMADDWD instruction.

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  64a0af2

Commits on Dec 11, 2016

• [X86][AVX512] Add missing patterns for broadcast fallback in case load node has multiple uses (for v4i64 and v4f64).

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  159e7f5

Commits on Dec 6, 2016

• [X86][AVX512] Detect repeated constant patterns in BUILD_VECTOR suitable for broadcasting.

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  c700b40

Commits on Nov 16, 2016

• [X86][AVX512] Removing llvm x86 intrinsics for _mm_mask_move_{ss|sd} intrinsics.

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  49b9925

Commits on Nov 13, 2016

• [X86][AVX512] Removing llvm x86 intrinsics for _mm_mask_move_{ss|sd} intrinsics.

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  061d58f

• [X86][AVX512] Add patterns for all variants of VMOVSS/VMOVSD instructions.

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  0a21d7d

Commits on Sep 26, 2016

• [X86][avx512] Fix bug in masked compress store.

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  de3ef8a

Commits on Sep 13, 2016

• Remove MVT:i1 xor instruction before SELECT. (Performance improvement).

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  7dc5b7e

Commits on Aug 17, 2016

• Fix bug in DAGBuilder for getelementptr with expanded vector.

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  cbfe590

• First commit (test commit) - Adding empty line.

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  de2442a