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x86emul: vendor specific SYSENTER/SYSEXIT behavior in long mode
Intel CPUs permit both insns there while AMD ones don't. While at it also - drop the ring 0 check from SYSENTER handling - neither Intel's nor AMD's insn pages have any indication of #GP(0) getting raised when executed from ring 0, and trying it out in practice also confirms the check shouldn't be there, - move SYSENTER segment register writing until after the (in principle able to fail) MSR reads. Signed-off-by: Jan Beulich <[email protected]> Reviewed-by: Andrew Cooper <[email protected]>
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