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at32: compile test
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@rogerlz
rogerlz committed Jun 10, 2024
1 parent 2b46314 commit ac1a4a6
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Showing 7 changed files with 81 additions and 12 deletions.
7 changes: 5 additions & 2 deletions src/stm32/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ config MACH_N32G45x
config HAVE_STM32_USBFS
bool
default y if MACH_STM32F0x2 || MACH_STM32G0Bx || MACH_STM32L4 || MACH_STM32G4 || MACH_AT32F403
default y if (MACH_STM32F103 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL
default y if (MACH_STM32F1 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL
config HAVE_STM32_USBOTG
bool
default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32H7
Expand Down Expand Up @@ -192,6 +192,7 @@ config MCU
default "stm32h743xx" if MACH_STM32H743
default "stm32h750xx" if MACH_STM32H750
default "stm32l412xx" if MACH_STM32L412
default "stm32f103xe" if MACH_N32G45x
default "AT32F403Axx" if MACH_AT32F403

config CLOCK_FREQ
Expand All @@ -209,6 +210,8 @@ config CLOCK_FREQ
default 170000000 if MACH_STM32G474
default 400000000 if MACH_STM32H7 # 400Mhz is max Klipper currently supports
default 80000000 if MACH_STM32L412
default 64000000 if MACH_N32G45x && STM32_CLOCK_REF_INTERNAL
default 128000000 if MACH_N32G45x
default 240000000 if MACH_AT32F403

config FLASH_SIZE
Expand Down Expand Up @@ -271,7 +274,7 @@ config STM32_DFU_ROM_ADDRESS
default 0 if !USB
default 0x1fffc400 if MACH_STM32F042
default 0x1fffc800 if MACH_STM32F072
default 0x1fff0000 if MACH_STM32F4 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
default 0x1fff0000 if MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
default 0x1fffb000 if MACH_AT32F403
default 0x1ff09800 if MACH_STM32H7
default 0
Expand Down
4 changes: 3 additions & 1 deletion src/stm32/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,9 @@ MCU := $(shell echo $(CONFIG_MCU))
MCU_UPPER := $(shell echo $(CONFIG_MCU) | tr a-z A-Z | tr X x)

CFLAGS-$(CONFIG_MACH_STM32F0) += -mcpu=cortex-m0 -Ilib/stm32f0/include
CFLAGS-$(CONFIG_MACH_STM32F1) += -mcpu=cortex-m4 -Ilib/stm32f1/include
CFLAGS-$(CONFIG_MACH_STM32F103) += -mcpu=cortex-m3
CFLAGS-$(CONFIG_MACH_N32G45x) += -mcpu=cortex-m4 -Ilib/n32g45x/include
CFLAGS-$(CONFIG_MACH_STM32F1) += -Ilib/stm32f1/include
CFLAGS-$(CONFIG_MACH_STM32F2) += -mcpu=cortex-m3 -Ilib/stm32f2/include
CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include
CFLAGS-$(CONFIG_MACH_STM32F7) += -mcpu=cortex-m7 -Ilib/stm32f7/include
Expand Down
65 changes: 64 additions & 1 deletion src/stm32/hard_pwm.c
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Expand Up @@ -20,7 +20,70 @@ struct gpio_pwm_info {
};

static const struct gpio_pwm_info pwm_regs[] = {
#if CONFIG_MACH_STM32F103 || CONFIG_MACH_AT32F403
#if CONFIG_MACH_STM32F0
#if CONFIG_MACH_STM32F070
{TIM15, GPIO('A', 2), 1, GPIO_FUNCTION(0)},
{TIM15, GPIO('A', 3), 2, GPIO_FUNCTION(0)},
{TIM14, GPIO('A', 4), 1, GPIO_FUNCTION(4)},
{TIM3, GPIO('A', 6), 1, GPIO_FUNCTION(1)},
{TIM3, GPIO('A', 7), 2, GPIO_FUNCTION(1)},
{TIM1, GPIO('A', 8), 1, GPIO_FUNCTION(2)},
{TIM1, GPIO('A', 9), 2, GPIO_FUNCTION(2)},
{TIM1, GPIO('A', 10), 3, GPIO_FUNCTION(2)},
{TIM1, GPIO('A', 11), 4, GPIO_FUNCTION(2)},
{TIM3, GPIO('B', 0), 3, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 1), 4, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 5), 2, GPIO_FUNCTION(1)},
{TIM16, GPIO('B', 8), 1, GPIO_FUNCTION(2)},
{TIM17, GPIO('B', 9), 1, GPIO_FUNCTION(2)},
{TIM15, GPIO('B', 14), 1, GPIO_FUNCTION(1)},
{TIM15, GPIO('B', 15), 2, GPIO_FUNCTION(1)},
{TIM3, GPIO('C', 6), 1, GPIO_FUNCTION(0)},
{TIM3, GPIO('C', 7), 2, GPIO_FUNCTION(0)},
{TIM3, GPIO('C', 8), 3, GPIO_FUNCTION(0)},
{TIM3, GPIO('C', 9), 4, GPIO_FUNCTION(0)}
#endif
#if CONFIG_MACH_STM32F072
{TIM2, GPIO('A', 1), 2, GPIO_FUNCTION(2)},
{TIM2, GPIO('A', 2), 3, GPIO_FUNCTION(2)},
{TIM2, GPIO('A', 3), 4, GPIO_FUNCTION(2)},
{TIM14, GPIO('A', 4), 1, GPIO_FUNCTION(4)},
{TIM3, GPIO('A', 6), 1, GPIO_FUNCTION(1)},
{TIM3, GPIO('A', 7), 2, GPIO_FUNCTION(1)},
{TIM1, GPIO('A', 8), 1, GPIO_FUNCTION(2)},
{TIM1, GPIO('A', 9), 2, GPIO_FUNCTION(2)},
{TIM1, GPIO('A', 10), 3, GPIO_FUNCTION(2)},
{TIM1, GPIO('A', 11), 4, GPIO_FUNCTION(2)},
{TIM3, GPIO('B', 0), 3, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 1), 4, GPIO_FUNCTION(1)},
{TIM2, GPIO('B', 3), 2, GPIO_FUNCTION(2)},
{TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)},
{TIM3, GPIO('B', 5), 2, GPIO_FUNCTION(1)},
{TIM16, GPIO('B', 8), 1, GPIO_FUNCTION(2)},
{TIM17, GPIO('B', 9), 1, GPIO_FUNCTION(2)},
{TIM2, GPIO('B', 10), 3, GPIO_FUNCTION(2)},
{TIM2, GPIO('B', 11), 4, GPIO_FUNCTION(2)},
{TIM15, GPIO('B', 14), 1, GPIO_FUNCTION(1)},
{TIM15, GPIO('B', 15), 2, GPIO_FUNCTION(1)},
{TIM3, GPIO('C', 6), 1, GPIO_FUNCTION(0)},
{TIM3, GPIO('C', 7), 2, GPIO_FUNCTION(0)},
{TIM3, GPIO('C', 8), 3, GPIO_FUNCTION(0)},
{TIM3, GPIO('C', 9), 4, GPIO_FUNCTION(0)},
{TIM16, GPIO('E', 0), 1, GPIO_FUNCTION(0)},
{TIM17, GPIO('E', 1), 1, GPIO_FUNCTION(0)},
{TIM3, GPIO('E', 3), 1, GPIO_FUNCTION(0)},
{TIM3, GPIO('E', 4), 2, GPIO_FUNCTION(0)},
{TIM3, GPIO('E', 5), 3, GPIO_FUNCTION(0)},
{TIM3, GPIO('E', 6), 4, GPIO_FUNCTION(0)},
{TIM1, GPIO('E', 9), 1, GPIO_FUNCTION(0)},
{TIM1, GPIO('E', 11), 2, GPIO_FUNCTION(0)},
{TIM1, GPIO('E', 13), 3, GPIO_FUNCTION(0)},
{TIM1, GPIO('E', 14), 4, GPIO_FUNCTION(0)},
{TIM15, GPIO('F', 9), 1, GPIO_FUNCTION(0)},
{TIM15, GPIO('F', 10), 2, GPIO_FUNCTION(0)}
#endif
#elif CONFIG_MACH_STM32F1
{TIM2, GPIO('A', 0), 1, GPIO_FUNCTION(2)},
{TIM2, GPIO('A', 1), 2, GPIO_FUNCTION(2)},
{TIM2, GPIO('A', 2), 3, GPIO_FUNCTION(2)},
Expand Down
5 changes: 3 additions & 2 deletions src/stm32/spi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -122,8 +122,9 @@ spi_prepare(struct spi_config config)
{
SPI_TypeDef *spi = config.spi;
uint32_t cr1 = spi->CR1;
//if (cr1 == config.spi_cr1)
// return;
if (! CONFIG_MACH_AT32F403)
if (cr1 == config.spi_cr1)
return;
// The SPE bit must be disabled before changing CPOL/CPHA bits
spi->CR1 = cr1 & ~SPI_CR1_SPE;
spi->CR1; // Force flush of previous write
Expand Down
7 changes: 2 additions & 5 deletions src/stm32/stm32f1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -77,12 +77,10 @@ clock_setup(void)
RCC->CR |= RCC_CR_HSEON;
uint32_t div = CONFIG_CLOCK_FREQ / (CONFIG_CLOCK_REF_FREQ / 2);
cfgr = 1 << RCC_CFGR_PLLSRC_Pos;

if ((div & 1) && div <= 16)
cfgr |= RCC_CFGR_PLLXTPRE_HSE_DIV2;
else
div /= 2;

if (div <= 16) {
cfgr |= (div - 2) << RCC_CFGR_PLLMULL_Pos;
} else { // only at32f4 exceeds 16
Expand Down Expand Up @@ -111,7 +109,8 @@ clock_setup(void)
RCC->CR |= RCC_CR_PLLON;

// Set flash latency
//FLASH->ACR = (2 << FLASH_ACR_LATENCY_Pos) | FLASH_ACR_PRFTBE;
if (! CONFIG_MACH_AT32F403)
FLASH->ACR = (2 << FLASH_ACR_LATENCY_Pos) | FLASH_ACR_PRFTBE;

// Wait for PLL lock
while (!(RCC->CR & RCC_CR_PLLRDY))
Expand Down Expand Up @@ -282,7 +281,6 @@ bootloader_request(void)
usb_hid_bootloader();
else if (CONFIG_STM32_FLASH_START_2000)
usb_stm32duino_bootloader();
dfu_reboot();
}


Expand All @@ -294,7 +292,6 @@ bootloader_request(void)
void
armcm_main(void)
{
dfu_reboot_check();
// Run SystemInit() and then restore VTOR
SystemInit();
SCB->VTOR = (uint32_t)VectorTable;
Expand Down
2 changes: 1 addition & 1 deletion src/stm32/usbfs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
#include "internal.h" // GPIO
#include "sched.h" // DECL_INIT

#if CONFIG_MACH_STM32F103 || CONFIG_MACH_STM32G4 || CONFIG_MACH_AT32F403
#if CONFIG_MACH_STM32F1
// Transfer memory is accessed with 32bits, but contains only 16bits of data
typedef volatile uint32_t epmword_t;
#define WSIZE 2
Expand Down
3 changes: 3 additions & 0 deletions test/configs/at32f403.config
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Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
# Base config file for AT32F403 ARM processor
CONFIG_MACH_STM32=y
CONFIG_MACH_AT32F403=y

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