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[X86] Fix some Clang-tidy modernize-use-using and Include What You Us…
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…e warnings; other minor fixes (NFC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314953 91177308-0d34-0410-b5e6-96231b3b80d8
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@EugeneZelenko
EugeneZelenko committed Oct 5, 2017
1 parent ac8ec29 commit 2646cf2
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Showing 9 changed files with 239 additions and 132 deletions.
46 changes: 41 additions & 5 deletions include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//==-- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h ---------*- C++ -*-==//
//===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
Expand All @@ -16,6 +16,22 @@
#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H

#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <cstddef>
#include <cstdint>

namespace llvm {

/// GlobalISel PatFrag Predicates
Expand Down Expand Up @@ -120,6 +136,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckNumOperands: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t Expected = MatchTable[CurrentIdx++];
Expand All @@ -132,6 +149,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckImmPredicate: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t Predicate = MatchTable[CurrentIdx++];
Expand Down Expand Up @@ -170,6 +188,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckRegBankForClass: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Expand All @@ -186,6 +205,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckComplexPattern: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Expand All @@ -205,6 +225,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckConstantInt: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Expand All @@ -220,6 +241,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckLiteralInt: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Expand All @@ -228,13 +250,14 @@ bool InstructionSelector::executeMatchTable(
<< "]->getOperand(" << OpIdx << "), Value=" << Value
<< ")\n");
assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
MachineOperand &OM = State.MIs[InsnID]->getOperand(OpIdx);
if (!OM.isCImm() || !OM.getCImm()->equalsInt(Value)) {
MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
if (!MO.isCImm() || !MO.getCImm()->equalsInt(Value)) {
if (handleReject() == RejectAndGiveUp)
return false;
}
break;
}

case GIM_CheckIntrinsicID: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Expand All @@ -243,12 +266,13 @@ bool InstructionSelector::executeMatchTable(
<< "]->getOperand(" << OpIdx << "), Value=" << Value
<< ")\n");
assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
MachineOperand &OM = State.MIs[InsnID]->getOperand(OpIdx);
if (!OM.isIntrinsicID() || OM.getIntrinsicID() != Value)
MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
if (handleReject() == RejectAndGiveUp)
return false;
break;
}

case GIM_CheckIsMBB: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Expand All @@ -261,6 +285,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_CheckIsSafeToFold: {
int64_t InsnID = MatchTable[CurrentIdx++];
DEBUG(dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs[" << InsnID
Expand All @@ -272,6 +297,7 @@ bool InstructionSelector::executeMatchTable(
}
break;
}

case GIM_Reject:
DEBUG(dbgs() << CurrentIdx << ": GIM_Reject");
if (handleReject() == RejectAndGiveUp)
Expand All @@ -292,6 +318,7 @@ bool InstructionSelector::executeMatchTable(
<< "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
break;
}

case GIR_BuildMI: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t Opcode = MatchTable[CurrentIdx++];
Expand All @@ -315,6 +342,7 @@ bool InstructionSelector::executeMatchTable(
<< "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
break;
}

case GIR_CopySubReg: {
int64_t NewInsnID = MatchTable[CurrentIdx++];
int64_t OldInsnID = MatchTable[CurrentIdx++];
Expand All @@ -328,6 +356,7 @@ bool InstructionSelector::executeMatchTable(
<< SubRegIdx << ")\n");
break;
}

case GIR_AddImplicitDef: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t RegNum = MatchTable[CurrentIdx++];
Expand All @@ -337,6 +366,7 @@ bool InstructionSelector::executeMatchTable(
<< "], " << RegNum << ")\n");
break;
}

case GIR_AddImplicitUse: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t RegNum = MatchTable[CurrentIdx++];
Expand All @@ -346,6 +376,7 @@ bool InstructionSelector::executeMatchTable(
<< "], " << RegNum << ")\n");
break;
}

case GIR_AddRegister: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t RegNum = MatchTable[CurrentIdx++];
Expand All @@ -355,6 +386,7 @@ bool InstructionSelector::executeMatchTable(
<< "], " << RegNum << ")\n");
break;
}

case GIR_AddImm: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t Imm = MatchTable[CurrentIdx++];
Expand All @@ -364,6 +396,7 @@ bool InstructionSelector::executeMatchTable(
<< Imm << ")\n");
break;
}

case GIR_ComplexRenderer: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t RendererID = MatchTable[CurrentIdx++];
Expand Down Expand Up @@ -402,6 +435,7 @@ bool InstructionSelector::executeMatchTable(
<< "], " << OpIdx << ", " << RCEnum << ")\n");
break;
}

case GIR_ConstrainSelectedInstOperands: {
int64_t InsnID = MatchTable[CurrentIdx++];
assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
Expand All @@ -412,6 +446,7 @@ bool InstructionSelector::executeMatchTable(
<< "])\n");
break;
}

case GIR_MergeMemOperands: {
int64_t InsnID = MatchTable[CurrentIdx++];
assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
Expand All @@ -428,6 +463,7 @@ bool InstructionSelector::executeMatchTable(
DEBUG(dbgs() << ")\n");
break;
}

case GIR_EraseFromParent: {
int64_t InsnID = MatchTable[CurrentIdx++];
assert(State.MIs[InsnID] &&
Expand Down
53 changes: 34 additions & 19 deletions lib/Target/X86/X86CallLowering.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,30 +1,50 @@
//===-- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering -----------===//
//===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
///
//
/// \file
/// This file implements the lowering of LLVM calls to machine code calls for
/// GlobalISel.
///
//
//===----------------------------------------------------------------------===//

#include "X86CallLowering.h"
#include "X86CallingConv.h"
#include "X86ISelLowering.h"
#include "X86InstrInfo.h"
#include "X86TargetMachine.h"

#include "X86RegisterInfo.h"
#include "X86Subtarget.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/LowLevelType.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/LowLevelTypeImpl.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>

using namespace llvm;

Expand All @@ -38,7 +58,6 @@ bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
const DataLayout &DL,
MachineRegisterInfo &MRI,
SplitArgTy PerformArgSplit) const {

const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
LLVMContext &Context = OrigArg.Ty->getContext();

Expand Down Expand Up @@ -79,16 +98,16 @@ bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
}

namespace {

struct OutgoingValueHandler : public CallLowering::ValueHandler {
OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), StackSize(0),
: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
DL(MIRBuilder.getMF().getDataLayout()),
STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()), NumXMMRegs(0) {}
STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}

unsigned getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO) override {

LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
unsigned SPReg = MRI.createGenericVirtualRegister(p0);
Expand All @@ -113,7 +132,6 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {

void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {

unsigned ExtReg = extendRegister(ValVReg, VA);
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
Expand All @@ -124,7 +142,6 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, CCState &State) override {

bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
StackSize = State.getNextStackOffset();

Expand All @@ -142,16 +159,16 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {

protected:
MachineInstrBuilder &MIB;
uint64_t StackSize;
uint64_t StackSize = 0;
const DataLayout &DL;
const X86Subtarget &STI;
unsigned NumXMMRegs;
unsigned NumXMMRegs = 0;
};
} // End anonymous namespace.

} // end anonymous namespace

bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, unsigned VReg) const {

assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");

auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
Expand Down Expand Up @@ -182,6 +199,7 @@ bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
}

namespace {

struct IncomingValueHandler : public CallLowering::ValueHandler {
IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn)
Expand All @@ -190,7 +208,6 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {

unsigned getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO) override {

auto &MFI = MIRBuilder.getMF().getFrameInfo();
int FI = MFI.CreateFixedObject(Size, Offset, true);
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
Expand All @@ -203,7 +220,6 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {

void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {

auto MMO = MIRBuilder.getMF().getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
0);
Expand Down Expand Up @@ -241,7 +257,7 @@ struct CallReturnHandler : public IncomingValueHandler {
MachineInstrBuilder &MIB;
};

} // namespace
} // end anonymous namespace

bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
Expand Down Expand Up @@ -299,7 +315,6 @@ bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const MachineOperand &Callee,
const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs) const {

MachineFunction &MF = MIRBuilder.getMF();
const Function &F = *MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
Expand Down
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