Regenerate documentation

nikolabebic95 · Aug 22, 2017 · 20974fd · 20974fd
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diff --git a/Documentation/Doxygen/html/_r_e_a_d_m_e_8md_source.html b/Documentation/Doxygen/html/_r_e_a_d_m_e_8md_source.html
diff --git a/Documentation/Doxygen/html/index.html b/Documentation/Doxygen/html/index.html
@@ -109,25 +109,35 @@ <h4>Flow control instructions</h4>
 <tr>
 <td><em><b>Instruction</b></em> </td><td><em><b>Address modes</b></em> </td><td><em><b>Comment</b></em>  </td></tr>
 <tr>
-<td><code>INT op</code> </td><td>Register direct </td><td>Generates a software interrupt. Interrupt entry is in the register  </td></tr>
+<td><code>INT op</code> </td><td>Register direct </td><td>Generates a software interrupt.<br />
+ Interrupt entry is in the register  </td></tr>
 <tr>
-<td><code>JMP op</code> </td><td>Memory direct, register indirect, register indirect with offset </td><td>Jumps to given address  </td></tr>
+<td><code>JMP op</code> </td><td>Memory direct, register indirect,<br />
+ register indirect with offset </td><td>Jumps to given address  </td></tr>
 <tr>
-<td><code>CALL op</code> </td><td>Memory direct, register indirect, register indirect with offset </td><td>Calls a subroutine. <code>PC</code> is pushed to the stack  </td></tr>
+<td><code>CALL op</code> </td><td>Memory direct, register indirect,<br />
+ register indirect with offset </td><td>Calls a subroutine.<br />
+ <code>PC</code> is pushed to the stack  </td></tr>
 <tr>
 <td><code>RET</code> </td><td>None </td><td>Returns from subroutine  </td></tr>
 <tr>
-<td><code>JZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg == 0</code>  </td></tr>
+<td><code>JZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br />
+ register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg == 0</code>  </td></tr>
 <tr>
-<td><code>JNZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg != 0</code>  </td></tr>
+<td><code>JNZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br />
+ register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg != 0</code>  </td></tr>
 <tr>
-<td><code>JGZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &gt; 0</code>  </td></tr>
+<td><code>JGZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br />
+ register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &gt; 0</code>  </td></tr>
 <tr>
-<td><code>JGEZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &gt;= 0</code>  </td></tr>
+<td><code>JGEZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br />
+ register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &gt;= 0</code>  </td></tr>
 <tr>
-<td><code>JLZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &lt; 0</code>  </td></tr>
+<td><code>JLZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br />
+ register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &lt; 0</code>  </td></tr>
 <tr>
-<td><code>JLEZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &lt; 0</code>  </td></tr>
+<td><code>JLEZ reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br />
+ register indirect, register indirect with offset </td><td>Jumps to <code>op</code> if <code>reg &lt; 0</code>  </td></tr>
 </table>
 <h3>Load/Store instructions</h3>
 <p>Load, sizes of operands:</p><ul>
@@ -149,7 +159,7 @@ <h3>Load/Store instructions</h3>
 <tr>
 <td><code>LOAD reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: All </td><td>Loads the data into the register  </td></tr>
 <tr>
-<td><code>STORE reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: All except Immediate </td><td>Stores the data from the register  </td></tr>
+<td><code>STORE reg, op</code> </td><td><code>reg</code>: Register direct, <code>op</code>: All except immediate </td><td>Stores the data from the register  </td></tr>
 </table>
 <h3>Stack instructions</h3>
 <ul>
@@ -161,7 +171,7 @@ <h3>Stack instructions</h3>
 <tr>
 <td><code>PUSH reg</code> </td><td>Register direct </td><td>Pushes the register to the stack  </td></tr>
 <tr>
-<td><code>STORE reg, op</code> </td><td>Register direct </td><td>Pops the register from the stack  </td></tr>
+<td><code>POP reg</code> </td><td>Register direct </td><td>Pops the register from the stack  </td></tr>
 </table>
 <h3>ALU instructions</h3>
 <ul>

diff --git a/Documentation/Doxygen/rtf/refman.rtf b/Documentation/Doxygen/rtf/refman.rtf
@@ -84,7 +84,7 @@
 {\info 
 {\title {\comment AssemblerEmulator - Nikola Bebic }AssemblerEmulator - Nikola Bebic}
 {\comment Generated byDoxgyen. }
-{\creatim \yr2017\mo8\dy22\hr14\min14\sec41}
+{\creatim \yr2017\mo8\dy22\hr14\min41\sec48}
 }\pard\plain 
 \sectd\pgnlcrm
 {\footer \s29\widctlpar\tqc\tx4320\tqr\tx8640\qr\adjustright \fs20\cgrid {\chpgn}}
@@ -252,23 +252,27 @@ Instruction format:\par
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 INT op}  \cell }{Register direct \cell }{Generates a software interrupt. Interrupt entry is in the register  \cell }
+{{\f2 INT op}  \cell }{Register direct \cell }{Generates a software interrupt.\par
+ Interrupt entry is in the register  \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JMP op}  \cell }{Memory direct, register indirect, register indirect with offset \cell }{Jumps to given address  \cell }
+{{\f2 JMP op}  \cell }{Memory direct, register indirect,\par
+ register indirect with offset \cell }{Jumps to given address  \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 CALL op}  \cell }{Memory direct, register indirect, register indirect with offset \cell }{Calls a subroutine. {\f2 PC}  is pushed to the stack  \cell }
+{{\f2 CALL op}  \cell }{Memory direct, register indirect,\par
+ register indirect with offset \cell }{Calls a subroutine.\par
+ {\f2 PC}  is pushed to the stack  \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
@@ -284,47 +288,53 @@ Instruction format:\par
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct, register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg == 0}   \cell }
+{{\f2 JZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct,\par
+ register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg == 0}   \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JNZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct, register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg != 0}   \cell }
+{{\f2 JNZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct,\par
+ register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg != 0}   \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JGZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct, register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg > 0}   \cell }
+{{\f2 JGZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct,\par
+ register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg > 0}   \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JGEZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct, register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg >= 0}   \cell }
+{{\f2 JGEZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct,\par
+ register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg >= 0}   \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JLZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct, register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg < 0}   \cell }
+{{\f2 JLZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct,\par
+ register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg < 0}   \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \trowd \trgaph108\trleft-108\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx2916
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 JLEZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct, register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg < 0}   \cell }
+{{\f2 JLEZ reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : Memory direct,\par
+ register indirect, register indirect with offset \cell }{Jumps to {\f2 op}  if {\f2 reg < 0}   \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \pard\plain
@@ -372,7 +382,7 @@ Size of word is 2 bytes, and size of double word is 2 words\par
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 STORE reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : All except Immediate \cell }{Stores the data from the register  \cell }
+{{\f2 STORE reg, op}  \cell }{{\f2 reg} : Register direct, {\f2 op} : All except immediate \cell }{Stores the data from the register  \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \pard\plain
@@ -403,7 +413,7 @@ Size of word is 2 bytes, and size of double word is 2 words\par
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx5832
 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb \cellx8748
 \pard \widctlpar\intbl\adjustright
-{{\f2 STORE reg, op}  \cell }{Register direct \cell }{Pops the register from the stack  \cell }
+{{\f2 POP reg}  \cell }{Register direct \cell }{Pops the register from the stack  \cell }
 \pard \widctlpar\intbl\adjustright
 {\row }
 \pard\plain

diff --git a/README.md b/README.md
@@ -156,17 +156,21 @@ Instruction format:
     <tr>
         <td><code>INT op</code></td>
         <td>Register direct</td>
-        <td>Generates a software interrupt. Interrupt entry is in the register</td>
+        <td>Generates a software interrupt.<br/>
+        Interrupt entry is in the register</td>
     </tr>
     <tr>
         <td><code>JMP op</code></td>
-        <td>Memory direct, register indirect, register indirect with offset</td>
+        <td>Memory direct, register indirect,<br/>
+        register indirect with offset</td>
         <td>Jumps to given address</td>
     </tr>
     <tr>
         <td><code>CALL op</code></td>
-        <td>Memory direct, register indirect, register indirect with offset</td>
-        <td>Calls a subroutine. <code>PC</code> is pushed to the stack</td>
+        <td>Memory direct, register indirect,<br/>
+        register indirect with offset</td>
+        <td>Calls a subroutine.<br/>
+        <code>PC</code> is pushed to the stack</td>
     </tr>
     <tr>
         <td><code>RET</code></td>
@@ -175,32 +179,38 @@ Instruction format:
     </tr>
     <tr>
         <td><code>JZ reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br/> 
+        register indirect, register indirect with offset</td>
         <td>Jumps to <code>op</code> if <code>reg == 0</code></td>
     </tr>
     <tr>
         <td><code>JNZ reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br/> 
+        register indirect, register indirect with offset</td>
         <td>Jumps to <code>op</code> if <code>reg != 0</code></td>
     </tr>
     <tr>
         <td><code>JGZ reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br/> 
+        register indirect, register indirect with offset</td>
         <td>Jumps to <code>op</code> if <code>reg > 0</code></td>
     </tr>
     <tr>
         <td><code>JGEZ reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br/>  
+        register indirect, register indirect with offset</td>
         <td>Jumps to <code>op</code> if <code>reg >= 0</code></td>
     </tr>
     <tr>
         <td><code>JLZ reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br/> 
+        register indirect, register indirect with offset</td>
         <td>Jumps to <code>op</code> if <code>reg < 0</code></td>
     </tr>
     <tr>
         <td><code>JLEZ reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct, register indirect, register indirect with offset</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: Memory direct,<br/> 
+        register indirect, register indirect with offset</td>
         <td>Jumps to <code>op</code> if <code>reg < 0</code></td>
     </tr>
 </table>
@@ -234,7 +244,7 @@ Size of word is 2 bytes, and size of double word is 2 words
     </tr>
     <tr>
         <td><code>STORE reg, op</code></td>
-        <td><code>reg</code>: Register direct, <code>op</code>: All except Immediate</td>
+        <td><code>reg</code>: Register direct, <code>op</code>: All except immediate</td>
         <td>Stores the data from the register</td>
     </tr>
 </table>
@@ -255,7 +265,7 @@ Size of word is 2 bytes, and size of double word is 2 words
         <td>Pushes the register to the stack</td>
     </tr>
     <tr>
-        <td><code>STORE reg, op</code></td>
+        <td><code>POP reg</code></td>
         <td>Register direct</td>
         <td>Pops the register from the stack</td>
     </tr>