《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

SPI Slave for FPGA in Verilog and VHDL

JESD204B ADC and DAC SYZYGY Pod.

FMC ADC 4x1GS/s 12B JESD204B

Implementation of JESD204B Transport Layer & part of Data Link Layer

ICE40 FPGA configuration: SSD1306 to VGA converter

FPGA controller for SSD1306 OLED module on SPI. Optimised for GOWIN FPGA

FPGA driver of step motor on CIC-560 training system designing for plazmatrone sample 1-d positioning

关于CIC滤波器、ISOP补偿器、HB滤波器的相关Matlab仿真与FPGA工程

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

Video streaming at FPGA using OV2640

本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。

上位机软件与下位机FPGA采集卡实现UDP通信，接收发送的正弦波信号帧，并保存到本地文件

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA

An HDL design for sending data over Ethernet

This repo is about implementing OFDM transmitter on FPGA (Zedboard) using Verilog language and Vivado simulator

Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Functio…

Using the Quartus II software, a OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Function…

Toy OFDM Communication System with FPGA

This repo is for ECE44x (Fall2015-Spring2016)

一个FPGA核心板设计，体积小、低成本、易用、扩展性强。

FPGA display controller with support for VGA, DVI, and HDMI.

Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board

A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark

IP operations in verilog (simulation and implementation on ice40)

基于HLS的高效深度卷积神经网络FPGA实现方法