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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/lin…
…ux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "The irq department provides: - Support for MSI to wire bridges and a first user of it - More ACPI support for ARM/GIC - A new TS-4800 interrupt controller driver - RCU based free of interrupt descriptors to support the upcoming Intel VMD technology without introducing a locking nightmare - The usual pile of fixes and updates to drivers and core code" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits) irqchip/omap-intc: Add support for spurious irq handling irqchip/zevio: Use irq_data_get_chip_type() helper irqchip/omap-intc: Remove duplicate setup for IRQ chip type handler irqchip/ts4800: Add TS-4800 interrupt controller irqchip/ts4800: Add documentation for TS-4800 interrupt controller irq/platform-MSI: Increase the maximum MSIs the MSI framework can support irqchip/gicv2m: Miscellaneous fixes for v2m resources and SPI ranges irqchip/bcm2836: Make code more readable irqchip/bcm2836: Tolerate IRQs while no flag is set in ISR irqchip/bcm2836: Add SMP support for the 2836 irqchip/bcm2836: Fix initialization of the LOCAL_IRQ_CNT timers irqchip/gic-v2m: acpi: Introducing GICv2m ACPI support irqchip/gic-v2m: Refactor to prepare for ACPI support irqdomain: Introduce is_fwnode_irqchip helper acpi: pci: Setup MSI domain for ACPI based pci devices genirq/msi: Export functions to allow MSI domains in modules irqchip/mbigen: Implement the mbigen irq chip operation functions irqchip/mbigen: Create irq domain for each mbigen device irqchip/mgigen: Add platform device driver for mbigen device dt-bindings: Documents the mbigen bindings ...
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Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
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Hisilicon mbigen device tree bindings. | ||
======================================= | ||
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Mbigen means: message based interrupt generator. | ||
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MBI is kind of msi interrupt only used on Non-PCI devices. | ||
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To reduce the wired interrupt number connected to GIC, | ||
Hisilicon designed mbigen to collect and generate interrupt. | ||
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Non-pci devices can connect to mbigen and generate the | ||
interrupt by writing ITS register. | ||
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The mbigen chip and devices connect to mbigen have the following properties: | ||
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Mbigen main node required properties: | ||
------------------------------------------- | ||
- compatible: Should be "hisilicon,mbigen-v2" | ||
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- reg: Specifies the base physical address and size of the Mbigen | ||
registers. | ||
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- interrupt controller: Identifies the node as an interrupt controller | ||
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- msi-parent: Specifies the MSI controller this mbigen use. | ||
For more detail information,please refer to the generic msi-parent binding in | ||
Documentation/devicetree/bindings/interrupt-controller/msi.txt. | ||
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- num-pins: the total number of pins implemented in this Mbigen | ||
instance. | ||
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- #interrupt-cells : Specifies the number of cells needed to encode an | ||
interrupt source. The value must be 2. | ||
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The 1st cell is hardware pin number of the interrupt.This number is local to | ||
each mbigen chip and in the range from 0 to the maximum interrupts number | ||
of the mbigen. | ||
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The 2nd cell is the interrupt trigger type. | ||
The value of this cell should be: | ||
1: rising edge triggered | ||
or | ||
4: high level triggered | ||
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Examples: | ||
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mbigen_device_gmac:intc { | ||
compatible = "hisilicon,mbigen-v2"; | ||
reg = <0x0 0xc0080000 0x0 0x10000>; | ||
interrupt-controller; | ||
msi-parent = <&its_dsa 0x40b1c>; | ||
num-pins = <9>; | ||
#interrupt-cells = <2>; | ||
}; | ||
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Devices connect to mbigen required properties: | ||
---------------------------------------------------- | ||
-interrupt-parent: Specifies the mbigen device node which device connected. | ||
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-interrupts:Specifies the interrupt source. | ||
For the specific information of each cell in this property,please refer to | ||
the "interrupt-cells" description mentioned above. | ||
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Examples: | ||
gmac0: ethernet@c2080000 { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0 0xc2080000 0 0x20000>, | ||
<0 0xc0000000 0 0x1000>; | ||
interrupt-parent = <&mbigen_device_gmac>; | ||
interrupts = <656 1>, | ||
<657 1>; | ||
}; |
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Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt
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TS-4800 FPGA interrupt controller | ||
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TS-4800 FPGA has an internal interrupt controller. When one of the | ||
interrupts is triggered, the SoC is notified, usually using a GPIO as | ||
parent interrupt source. | ||
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Required properties: | ||
- compatible: should be "technologic,ts4800-irqc" | ||
- interrupt-controller: identifies the node as an interrupt controller | ||
- reg: physical base address of the controller and length of memory mapped | ||
region | ||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt | ||
source, should be 1. | ||
- interrupt-parent: phandle to the parent interrupt controller this one is | ||
cascaded from | ||
- interrupts: specifies the interrupt line in the interrupt-parent controller |
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