forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge tag 'soc-drivers-6.4' of git://git.kernel.org/pub/scm/linux/ker…
…nel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "The most notable updates this time are for Qualcomm Snapdragon platforms. The Inline-Crypto-Engine gets a new DT binding and driver, and a number of drivers now support additional Snapdragon variants, in particular the rsc, scm, geni, bwm, glink and socinfo, while the llcc (edac) and rpm drivers get notable functionality updates. Updates on other platforms include: - Various updates to the Mediatek mutex and mmsys drivers, including support for the Helio X10 SoC - Support for unidirectional mailbox channels in Arm SCMI firmware - Support for per cpu asynchronous notification in OP-TEE firmware - Minor updates for memory controller drivers. - Minor updates for Renesas, TI, Amlogic, Apple, Broadcom, Tegra, Allwinner, Versatile Express, Canaan, Microchip, Mediatek and i.MX SoC drivers, mainly updating the use of MODULE_LICENSE() macros and obsolete DT driver interfaces" * tag 'soc-drivers-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) soc: ti: smartreflex: Simplify getting the opam_sr pointer bus: vexpress-config: Add explicit of_platform.h include soc: mediatek: Kconfig: Add MTK_CMDQ dependency to MTK_MMSYS memory: mtk-smi: mt8365: Add SMI Support dt-bindings: memory-controllers: mediatek,smi-larb: add mt8365 dt-bindings: memory-controllers: mediatek,smi-common: add mt8365 memory: tegra: read values from correct device dt-bindings: crypto: Add Qualcomm Inline Crypto Engine soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver dt-bindings: firmware: document Qualcomm QCM2290 SCM soc: qcom: rpmh-rsc: Support RSC v3 minor versions soc: qcom: smd-rpm: Use GFP_ATOMIC in write path soc/tegra: fuse: Remove nvmem root only access soc/tegra: cbb: tegra194: Use of_address_count() helper soc/tegra: cbb: Remove MODULE_LICENSE in non-modules ARM: tegra: Remove MODULE_LICENSE in non-modules soc/tegra: flowctrl: Use devm_platform_get_and_ioremap_resource() soc: tegra: cbb: Drop empty platform remove function firmware: arm_scmi: Add support for unidirectional mailbox channels dt-bindings: firmware: arm,scmi: Support mailboxes unidirectional channels ...
- Loading branch information
Showing
129 changed files
with
3,008 additions
and
2,013 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
4 changes: 2 additions & 2 deletions
4
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# | |
title: Last Level Cache Controller | ||
|
||
maintainers: | ||
- Rishabh Bhatnagar <[email protected]> | ||
- Sai Prakash Ranjan <[email protected]> | ||
- Bjorn Andersson <[email protected]> | ||
|
||
description: | | ||
LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, | ||
|
@@ -27,21 +26,20 @@ properties: | |
- qcom,sc8280xp-llcc | ||
- qcom,sdm845-llcc | ||
- qcom,sm6350-llcc | ||
- qcom,sm7150-llcc | ||
- qcom,sm8150-llcc | ||
- qcom,sm8250-llcc | ||
- qcom,sm8350-llcc | ||
- qcom,sm8450-llcc | ||
- qcom,sm8550-llcc | ||
|
||
reg: | ||
items: | ||
- description: LLCC base register region | ||
- description: LLCC broadcast base register region | ||
minItems: 2 | ||
maxItems: 9 | ||
|
||
reg-names: | ||
items: | ||
- const: llcc_base | ||
- const: llcc_broadcast_base | ||
minItems: 2 | ||
maxItems: 9 | ||
|
||
interrupts: | ||
maxItems: 1 | ||
|
@@ -51,15 +49,120 @@ required: | |
- reg | ||
- reg-names | ||
|
||
allOf: | ||
- if: | ||
properties: | ||
compatible: | ||
contains: | ||
enum: | ||
- qcom,sc7180-llcc | ||
- qcom,sm6350-llcc | ||
then: | ||
properties: | ||
reg: | ||
items: | ||
- description: LLCC0 base register region | ||
- description: LLCC broadcast base register region | ||
reg-names: | ||
items: | ||
- const: llcc0_base | ||
- const: llcc_broadcast_base | ||
|
||
- if: | ||
properties: | ||
compatible: | ||
contains: | ||
enum: | ||
- qcom,sc7280-llcc | ||
then: | ||
properties: | ||
reg: | ||
items: | ||
- description: LLCC0 base register region | ||
- description: LLCC1 base register region | ||
- description: LLCC broadcast base register region | ||
reg-names: | ||
items: | ||
- const: llcc0_base | ||
- const: llcc1_base | ||
- const: llcc_broadcast_base | ||
|
||
- if: | ||
properties: | ||
compatible: | ||
contains: | ||
enum: | ||
- qcom,sc8180x-llcc | ||
- qcom,sc8280xp-llcc | ||
then: | ||
properties: | ||
reg: | ||
items: | ||
- description: LLCC0 base register region | ||
- description: LLCC1 base register region | ||
- description: LLCC2 base register region | ||
- description: LLCC3 base register region | ||
- description: LLCC4 base register region | ||
- description: LLCC5 base register region | ||
- description: LLCC6 base register region | ||
- description: LLCC7 base register region | ||
- description: LLCC broadcast base register region | ||
reg-names: | ||
items: | ||
- const: llcc0_base | ||
- const: llcc1_base | ||
- const: llcc2_base | ||
- const: llcc3_base | ||
- const: llcc4_base | ||
- const: llcc5_base | ||
- const: llcc6_base | ||
- const: llcc7_base | ||
- const: llcc_broadcast_base | ||
|
||
- if: | ||
properties: | ||
compatible: | ||
contains: | ||
enum: | ||
- qcom,sdm845-llcc | ||
- qcom,sm8150-llcc | ||
- qcom,sm8250-llcc | ||
- qcom,sm8350-llcc | ||
- qcom,sm8450-llcc | ||
then: | ||
properties: | ||
reg: | ||
items: | ||
- description: LLCC0 base register region | ||
- description: LLCC1 base register region | ||
- description: LLCC2 base register region | ||
- description: LLCC3 base register region | ||
- description: LLCC broadcast base register region | ||
reg-names: | ||
items: | ||
- const: llcc0_base | ||
- const: llcc1_base | ||
- const: llcc2_base | ||
- const: llcc3_base | ||
- const: llcc_broadcast_base | ||
|
||
additionalProperties: false | ||
|
||
examples: | ||
- | | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
system-cache-controller@1100000 { | ||
compatible = "qcom,sdm845-llcc"; | ||
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; | ||
reg-names = "llcc_base", "llcc_broadcast_base"; | ||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; | ||
soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
system-cache-controller@1100000 { | ||
compatible = "qcom,sdm845-llcc"; | ||
reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, | ||
<0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, | ||
<0 0x01300000 0 0x50000>; | ||
reg-names = "llcc0_base", "llcc1_base", "llcc2_base", | ||
"llcc3_base", "llcc_broadcast_base"; | ||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; | ||
}; | ||
}; |
42 changes: 42 additions & 0 deletions
42
Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,42 @@ | ||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
||
title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine | ||
|
||
maintainers: | ||
- Bjorn Andersson <[email protected]> | ||
|
||
properties: | ||
compatible: | ||
items: | ||
- enum: | ||
- qcom,sm8550-inline-crypto-engine | ||
- const: qcom,inline-crypto-engine | ||
|
||
reg: | ||
maxItems: 1 | ||
|
||
clocks: | ||
maxItems: 1 | ||
|
||
required: | ||
- compatible | ||
- reg | ||
- clocks | ||
|
||
additionalProperties: false | ||
|
||
examples: | ||
- | | ||
#include <dt-bindings/clock/qcom,sm8550-gcc.h> | ||
crypto@1d88000 { | ||
compatible = "qcom,sm8550-inline-crypto-engine", | ||
"qcom,inline-crypto-engine"; | ||
reg = <0x01d88000 0x8000>; | ||
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; | ||
}; | ||
... |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
4 changes: 2 additions & 2 deletions
4
Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.