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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upst…
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…ream-linus

Pull MIPS updates from James Hogan:
 "math-emu:
   - Add missing clearing of BLTZALL and BGEZALL emulation counters
   - Fix BC1EQZ and BC1NEZ condition handling
   - Fix BLEZL and BGTZL identification

  BPF:
   - Add JIT support for SKF_AD_HATYPE
   - Use unsigned access for unsigned SKB fields
   - Quit clobbering callee saved registers in JIT code
   - Fix multiple problems in JIT skb access helpers

  Loongson 3:
   - Select MIPS_L1_CACHE_SHIFT_6

  Octeon:
   - Remove vestiges of CONFIG_CAVIUM_OCTEON_2ND_KERNEL
   - Remove unused L2C types and macros.
   - Remove unused SLI types and macros.
   - Fix compile error when USB is not enabled.
   - Octeon: Remove unused PCIERCX types and macros.
   - Octeon: Clean up platform code.

  SNI:
   - Remove recursive include of cpu-feature-overrides.h

  Sibyte:
   - Export symbol periph_rev to sb1250-mac network driver.
   - Fix Kconfig warning.

  Generic platform:
   - Enable Root FS on NFS in generic_defconfig

  SMP-MT:
   - Use CPU interrupt controller IPI IRQ domain support

  UASM:
   - Add support for LHU for uasm.
   - Remove needless ISA abstraction

  mm:
   - Add 48-bit VA space and 4-level page tables for 4K pages.

  PCI:
   - Add controllers before the specified head

  irqchip driver for MIPS CPU:
   - Replace magic 0x100 with IE_SW0
   - Prepare for non-legacy IRQ domains
   - Introduce IPI IRQ domain support

  MAINTAINERS:
   - Update email-id of Rahul Bedarkar

  NET:
   - sb1250-mac: Add missing MODULE_LICENSE()

  CPUFREQ:
   - Loongson2: drop set_cpus_allowed_ptr()

  Misc:
   - Disable Werror when W= is set
   - Opt into HAVE_COPY_THREAD_TLS
   - Enable GENERIC_CPU_AUTOPROBE
   - Use common outgoing-CPU-notification code
   - Remove dead define of ST_OFF
   - Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
   - Stengthen IPI IRQ domain sanity check
   - Remove confusing else statement in __do_page_fault()
   - Don't unnecessarily include kmalloc.h into <asm/cache.h>.
   - Delete unused definition of SMP_CACHE_SHIFT.
   - Delete redundant definition of SMP_CACHE_BYTES"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (39 commits)
  MIPS: Sibyte: Fix Kconfig warning.
  MIPS: Sibyte: Export symbol periph_rev to sb1250-mac network driver.
  NET: sb1250-mac: Add missing MODULE_LICENSE()
  MAINTAINERS: Update email-id of Rahul Bedarkar
  MIPS: Remove confusing else statement in __do_page_fault()
  MIPS: Stengthen IPI IRQ domain sanity check
  MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support
  irqchip: mips-cpu: Introduce IPI IRQ domain support
  irqchip: mips-cpu: Prepare for non-legacy IRQ domains
  irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
  MIPS: Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
  MIPS: generic: Enable Root FS on NFS in generic_defconfig
  MIPS: mach-rm: Remove recursive include of cpu-feature-overrides.h
  MIPS: Opt into HAVE_COPY_THREAD_TLS
  CPUFREQ: Loongson2: drop set_cpus_allowed_ptr()
  MIPS: uasm: Remove needless ISA abstraction
  MIPS: Remove dead define of ST_OFF
  MIPS: Use common outgoing-CPU-notification code
  MIPS: math-emu: Fix BC1EQZ and BC1NEZ condition handling
  MIPS: r2-on-r6-emu: Clear BLTZALL and BGEZALL debugfs counters
  ...
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@torvalds
torvalds committed May 12, 2017
2 parents 0ba1c19 + 3e44184 commit ac3c4aa
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2 changes: 1 addition & 1 deletion MAINTAINERS
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Original file line number Diff line number Diff line change
Expand Up @@ -7923,7 +7923,7 @@ L: [email protected]
S: Maintained

MARDUK (CREATOR CI40) DEVICE TREE SUPPORT
M: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
M: Rahul Bedarkar <rahulbedarkar89@gmail.com>
L: [email protected]
S: Maintained
F: arch/mips/boot/dts/img/pistachio_marduk.dts
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2 changes: 2 additions & 0 deletions arch/mips/Kbuild
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Original file line number Diff line number Diff line change
@@ -1,7 +1,9 @@
# Fail on warnings - also for files referenced in subdirs
# -Werror can be disabled for specific files using:
# CFLAGS_<file.o> := -Wno-error
ifeq ($(W),)
subdir-ccflags-y := -Werror
endif

# platform specific definitions
include arch/mips/Kbuild.platforms
Expand Down
24 changes: 11 additions & 13 deletions arch/mips/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ config MIPS
select ARCH_DISCARD_MEMBLOCK
select GENERIC_SMP_IDLE_THREAD
select BUILDTIME_EXTABLE_SORT
select GENERIC_CPU_AUTOPROBE
select GENERIC_CLOCKEVENTS
select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
select GENERIC_CMOS_UPDATE
Expand All @@ -68,6 +69,7 @@ config MIPS
select HANDLE_DOMAIN_IRQ
select HAVE_EXIT_THREAD
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_COPY_THREAD_TLS

menu "Machine selection"

Expand Down Expand Up @@ -1039,14 +1041,6 @@ config RWSEM_GENERIC_SPINLOCK
config RWSEM_XCHGADD_ALGORITHM
bool

config ARCH_HAS_ILOG2_U32
bool
default n

config ARCH_HAS_ILOG2_U64
bool
default n

config GENERIC_HWEIGHT
bool
default y
Expand Down Expand Up @@ -1372,6 +1366,7 @@ config CPU_LOONGSON3
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select MIPS_PGD_C0_CONTEXT
select MIPS_L1_CACHE_SHIFT_6
select GPIOLIB
help
The Loongson 3 processor implements the MIPS64R2 instruction
Expand Down Expand Up @@ -2120,10 +2115,13 @@ config MIPS_VA_BITS_48
bool "48 bits virtual memory"
depends on 64BIT
help
Support a maximum at least 48 bits of application virtual memory.
Default is 40 bits or less, depending on the CPU.
This option result in a small memory overhead for page tables.
This option is only supported with 16k and 64k page sizes.
Support a maximum at least 48 bits of application virtual
memory. Default is 40 bits or less, depending on the CPU.
For page sizes 16k and above, this option results in a small
memory overhead for page tables. For 4k page size, a fourth
level of page tables is added which imposes both a memory
overhead as well as slower TLB fault handling.

If unsure, say N.

choice
Expand All @@ -2133,7 +2131,6 @@ choice
config PAGE_SIZE_4KB
bool "4kB"
depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
depends on !MIPS_VA_BITS_48
help
This option select the standard 4kB Linux page size. On some
R3000-family processors this is the only available page size. Using
Expand Down Expand Up @@ -2982,6 +2979,7 @@ config HAVE_LATENCYTOP_SUPPORT

config PGTABLE_LEVELS
int
default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
default 3 if 64BIT && !PAGE_SIZE_64KB
default 2

Expand Down
2 changes: 1 addition & 1 deletion arch/mips/Kconfig.debug
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ config CMDLINE_OVERRIDE
config SB1XXX_CORELIS
bool "Corelis Debugger"
depends on SIBYTE_SB1xxx_SOC
select DEBUG_INFO
select DEBUG_INFO if !COMPILE_TEST
help
Select compile flags that produce code that can be processed by the
Corelis mksym utility and UDB Emulator.
Expand Down
9 changes: 0 additions & 9 deletions arch/mips/cavium-octeon/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -25,15 +25,6 @@ endif # CPU_CAVIUM_OCTEON

if CAVIUM_OCTEON_SOC

config CAVIUM_OCTEON_2ND_KERNEL
bool "Build the kernel to be used as a 2nd kernel on the same chip"
default "n"
help
This option configures this kernel to be linked at a different
address and use the 2nd uart for output. This allows a kernel built
with this option to be run at the same time as one built without this
option.

config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
Expand Down
4 changes: 0 additions & 4 deletions arch/mips/cavium-octeon/Platform
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,4 @@
platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000
else
load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000
endif
139 changes: 56 additions & 83 deletions arch/mips/cavium-octeon/executive/cvmx-l2c.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
* Contact: [email protected]
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
* Copyright (c) 2003-2017 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
Expand Down Expand Up @@ -239,6 +239,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
else {
uint64_t counter = 0;
int tad;

for (tad = 0; tad < CVMX_L2C_TADS; tad++)
counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
return counter;
Expand All @@ -249,6 +250,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
else {
uint64_t counter = 0;
int tad;

for (tad = 0; tad < CVMX_L2C_TADS; tad++)
counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
return counter;
Expand All @@ -259,6 +261,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
else {
uint64_t counter = 0;
int tad;

for (tad = 0; tad < CVMX_L2C_TADS; tad++)
counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
return counter;
Expand All @@ -270,6 +273,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
else {
uint64_t counter = 0;
int tad;

for (tad = 0; tad < CVMX_L2C_TADS; tad++)
counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
return counter;
Expand Down Expand Up @@ -301,7 +305,7 @@ static void fault_in(uint64_t addr, int len)
*/
CVMX_DCACHE_INVALIDATE;
while (len > 0) {
ACCESS_ONCE(*ptr);
READ_ONCE(*ptr);
len -= CVMX_CACHE_LINE_SIZE;
ptr += CVMX_CACHE_LINE_SIZE;
}
Expand Down Expand Up @@ -375,7 +379,9 @@ int cvmx_l2c_lock_line(uint64_t addr)
if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;

lckbase.s.lck_base = addr_tmp >> 7;

} else {
lckbase.s.lck_base = addr >> 7;
}
Expand Down Expand Up @@ -435,6 +441,7 @@ void cvmx_l2c_flush(void)
/* These may look like constants, but they aren't... */
int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;

for (set = 0; set < n_set; set++) {
for (assoc = 0; assoc < n_assoc; assoc++) {
address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
Expand Down Expand Up @@ -519,89 +526,49 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
union __cvmx_l2c_tag {
uint64_t u64;
struct cvmx_l2c_tag_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved:40;
uint64_t V:1; /* Line valid */
uint64_t D:1; /* Line dirty */
uint64_t L:1; /* Line locked */
uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:20; /* Phys mem addr (33..14) */
#else
uint64_t addr:20; /* Phys mem addr (33..14) */
uint64_t U:1; /* Use, LRU eviction */
uint64_t L:1; /* Line locked */
uint64_t D:1; /* Line dirty */
uint64_t V:1; /* Line valid */
uint64_t reserved:40;
#endif
__BITFIELD_FIELD(uint64_t reserved:40,
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
__BITFIELD_FIELD(uint64_t addr:20, /* Phys addr (33..14) */
;))))))
} cn50xx;
struct cvmx_l2c_tag_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved:41;
uint64_t V:1; /* Line valid */
uint64_t D:1; /* Line dirty */
uint64_t L:1; /* Line locked */
uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:19; /* Phys mem addr (33..15) */
#else
uint64_t addr:19; /* Phys mem addr (33..15) */
uint64_t U:1; /* Use, LRU eviction */
uint64_t L:1; /* Line locked */
uint64_t D:1; /* Line dirty */
uint64_t V:1; /* Line valid */
uint64_t reserved:41;
#endif
__BITFIELD_FIELD(uint64_t reserved:41,
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
__BITFIELD_FIELD(uint64_t addr:19, /* Phys addr (33..15) */
;))))))
} cn30xx;
struct cvmx_l2c_tag_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved:42;
uint64_t V:1; /* Line valid */
uint64_t D:1; /* Line dirty */
uint64_t L:1; /* Line locked */
uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:18; /* Phys mem addr (33..16) */
#else
uint64_t addr:18; /* Phys mem addr (33..16) */
uint64_t U:1; /* Use, LRU eviction */
uint64_t L:1; /* Line locked */
uint64_t D:1; /* Line dirty */
uint64_t V:1; /* Line valid */
uint64_t reserved:42;
#endif
__BITFIELD_FIELD(uint64_t reserved:42,
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
__BITFIELD_FIELD(uint64_t addr:18, /* Phys addr (33..16) */
;))))))
} cn31xx;
struct cvmx_l2c_tag_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved:43;
uint64_t V:1; /* Line valid */
uint64_t D:1; /* Line dirty */
uint64_t L:1; /* Line locked */
uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:17; /* Phys mem addr (33..17) */
#else
uint64_t addr:17; /* Phys mem addr (33..17) */
uint64_t U:1; /* Use, LRU eviction */
uint64_t L:1; /* Line locked */
uint64_t D:1; /* Line dirty */
uint64_t V:1; /* Line valid */
uint64_t reserved:43;
#endif
__BITFIELD_FIELD(uint64_t reserved:43,
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
__BITFIELD_FIELD(uint64_t addr:17, /* Phys addr (33..17) */
;))))))
} cn38xx;
struct cvmx_l2c_tag_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved:44;
uint64_t V:1; /* Line valid */
uint64_t D:1; /* Line dirty */
uint64_t L:1; /* Line locked */
uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:16; /* Phys mem addr (33..18) */
#else
uint64_t addr:16; /* Phys mem addr (33..18) */
uint64_t U:1; /* Use, LRU eviction */
uint64_t L:1; /* Line locked */
uint64_t D:1; /* Line dirty */
uint64_t V:1; /* Line valid */
uint64_t reserved:44;
#endif
__BITFIELD_FIELD(uint64_t reserved:44,
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
__BITFIELD_FIELD(uint64_t addr:16, /* Phys addr (33..18) */
;))))))
} cn58xx;
struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
Expand Down Expand Up @@ -629,8 +596,8 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
union __cvmx_l2c_tag tag_val;
uint64_t dbg_addr = CVMX_L2C_DBG;
unsigned long flags;

union cvmx_l2c_dbg debug_val;

debug_val.u64 = 0;
/*
* For low core count parts, the core number is always small
Expand Down Expand Up @@ -683,8 +650,8 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
{
union cvmx_l2c_tag tag;
tag.u64 = 0;

tag.u64 = 0;
if ((int)association >= cvmx_l2c_get_num_assoc()) {
cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
return tag;
Expand Down Expand Up @@ -767,17 +734,20 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr)

if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
union cvmx_l2c_ctl l2c_ctl;

l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
indxalias = !l2c_ctl.s.disidxalias;
} else {
union cvmx_l2c_cfg l2c_cfg;

l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
indxalias = l2c_cfg.s.idxalias;
}

if (indxalias) {
if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;

idx ^= idx / cvmx_l2c_get_num_sets();
idx ^= a_14_12;
} else {
Expand All @@ -801,6 +771,7 @@ int cvmx_l2c_get_cache_size_bytes(void)
int cvmx_l2c_get_set_bits(void)
{
int l2_set_bits;

if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
l2_set_bits = 11; /* 2048 sets */
else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
Expand Down Expand Up @@ -828,6 +799,7 @@ int cvmx_l2c_get_num_sets(void)
int cvmx_l2c_get_num_assoc(void)
{
int l2_assoc;

if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
OCTEON_IS_MODEL(OCTEON_CN52XX) ||
OCTEON_IS_MODEL(OCTEON_CN58XX) ||
Expand Down Expand Up @@ -869,16 +841,17 @@ int cvmx_l2c_get_num_assoc(void)
else if (mio_fus_dat3.s.l2c_crip == 1)
l2_assoc = 12;
} else {
union cvmx_l2d_fus3 val;
val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
uint64_t l2d_fus3;

l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3);
/*
* Using shifts here, as bit position names are
* different for each model but they all mean the
* same.
*/
if ((val.u64 >> 35) & 0x1)
if ((l2d_fus3 >> 35) & 0x1)
l2_assoc = l2_assoc >> 2;
else if ((val.u64 >> 34) & 0x1)
else if ((l2d_fus3 >> 34) & 0x1)
l2_assoc = l2_assoc >> 1;
}
return l2_assoc;
Expand Down
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