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Merge tag 'mfd-for-linus-4.11' of git://git.kernel.org/pub/scm/linux/…
…kernel/git/lee/mfd Pull MFD updates from Lee Jones: "Core Frameworks: - Add new !TOUCHSCREEN_SUN4I dependency for SUN4I_GPADC - List include/dt-bindings/mfd/* to files supported in MAINTAINERS New Drivers: - Intel Apollo Lake SPI NOR - ST STM32 Timers (Advanced, Basic and PWM) - Motorola 6556002 CPCAP (PMIC) New Device Support: - Add support for AXP221 to axp20x - Add support for Intel Gemini Lake to intel-lpss-pci - Add support for MT6323 LED to mt6397-core - Add support for COMe-bBD#, COMe-bSL6, COMe-bKL6, COMe-cAL6 and COMe-cKL6 to kempld-core New Functionality: - Add support for Analog CODAC to sun6i-prcm - Add support for Watchdog to lpc_ich Fix-ups: - Error handling improvements; axp288_charger, axp20x, ab8500-sysctrl - Adapt platform data handling; axp20x - IRQ handling improvements; arizona, axp20x - Remove superfluous code; arizona, axp20x, lpc_ich - Trivial coding style/spelling fixes; axp20x, abx500, mfd.txt - Regmap fix-ups; axp20x - DT changes; mfd.txt, aspeed-lpc, aspeed-gfx, ab8500-core, tps65912, mt6397 - Use new I2C probing mechanism; max77686 - Constification; rk808 Bug Fixes: - Stop data transfer whilst suspended; cros_ec" * tag 'mfd-for-linus-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (43 commits) mfd: lpc_ich: Enable watchdog on Intel Apollo Lake PCH mfd: lpc_ich: Remove useless comments in core part mfd: Add support for several boards to Kontron PLD driver mfd: constify regmap_irq_chip structures MAINTAINERS: Add include/dt-bindings/mfd to MFD entry mfd: cpcap: Add minimal support mfd: mt6397: Add MT6323 LED support into MT6397 driver Documentation: devicetree: Add LED subnode binding for MT6323 PMIC mfd: tps65912: Export OF device ID table as module aliases mfd: ab8500-core: Rename clock device and compatible mfd: cros_ec: Send correct suspend/resume event to EC mfd: max77686: Remove I2C device ID table mfd: max77686: Use the struct i2c_driver .probe_new instead of .probe mfd: max77686: Use of_device_get_match_data() helper mfd: max77686: Don't attempt to get i2c_device_id .data mfd: ab8500-sysctrl: Handle probe deferral mfd: intel-lpss: Add Intel Gemini Lake PCI IDs mfd: axp20x: Fix AXP806 access errors on cold boot mfd: cros_ec: Send suspend state notification to EC mfd: cros_ec: Prevent data transfer while device is suspended ...
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* Device tree bindings for Aspeed SoC Display Controller (GFX) | ||
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The Aspeed SoC Display Controller primarily does as its name suggests, but also | ||
participates in pinmux requests on the g5 SoCs. It is therefore considered a | ||
syscon device. | ||
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Required properties: | ||
- compatible: "aspeed,ast2500-gfx", "syscon" | ||
- reg: contains offset/length value of the GFX memory | ||
region. | ||
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Example: | ||
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gfx: display@1e6e6000 { | ||
compatible = "aspeed,ast2500-gfx", "syscon"; | ||
reg = <0x1e6e6000 0x1000>; | ||
}; |
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====================================================================== | ||
Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller | ||
====================================================================== | ||
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The LPC bus is a means to bridge a host CPU to a number of low-bandwidth | ||
peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The | ||
primary use case of the Aspeed LPC controller is as a slave on the bus | ||
(typically in a Baseboard Management Controller SoC), but under certain | ||
conditions it can also take the role of bus master. | ||
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The LPC controller is represented as a multi-function device to account for the | ||
mix of functionality it provides. The principle split is between the register | ||
layout at the start of the I/O space which is, to quote the Aspeed datasheet, | ||
"basically compatible with the [LPC registers from the] popular BMC controller | ||
H8S/2168[1]", and everything else, where everything else is an eclectic | ||
collection of functions with a esoteric register layout. "Everything else", | ||
here labeled the "host" portion of the controller, includes, but is not limited | ||
to: | ||
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* An IPMI Block Transfer[2] Controller | ||
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* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the | ||
physical properties of some LPC pins, configuration of serial IRQs, and | ||
APB-to-LPC bridging amonst other functions. | ||
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* An LPC Host Interface Controller: Manages functions exposed to the host such | ||
as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART | ||
management and bus snoop configuration. | ||
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* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom | ||
hardware management protocols for handover between the host and baseboard | ||
management controller. | ||
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Additionally the state of the LPC controller influences the pinmux | ||
configuration, therefore the host portion of the controller is exposed as a | ||
syscon as a means to arbitrate access. | ||
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[0] http://www.intel.com/design/chipsets/industry/25128901.pdf | ||
[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 | ||
[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf | ||
[3] https://en.wikipedia.org/wiki/Super_I/O | ||
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Required properties | ||
=================== | ||
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- compatible: One of: | ||
"aspeed,ast2400-lpc", "simple-mfd" | ||
"aspeed,ast2500-lpc", "simple-mfd" | ||
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- reg: contains the physical address and length values of the Aspeed | ||
LPC memory region. | ||
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- #address-cells: <1> | ||
- #size-cells: <1> | ||
- ranges: Maps 0 to the physical address and length of the LPC memory | ||
region | ||
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Required LPC Child nodes | ||
======================== | ||
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BMC Node | ||
-------- | ||
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- compatible: One of: | ||
"aspeed,ast2400-lpc-bmc" | ||
"aspeed,ast2500-lpc-bmc" | ||
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- reg: contains the physical address and length values of the | ||
H8S/2168-compatible LPC controller memory region | ||
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Host Node | ||
--------- | ||
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- compatible: One of: | ||
"aspeed,ast2400-lpc-host", "simple-mfd", "syscon" | ||
"aspeed,ast2500-lpc-host", "simple-mfd", "syscon" | ||
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- reg: contains the address and length values of the host-related | ||
register space for the Aspeed LPC controller | ||
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- #address-cells: <1> | ||
- #size-cells: <1> | ||
- ranges: Maps 0 to the address and length of the host-related LPC memory | ||
region | ||
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Example: | ||
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lpc: lpc@1e789000 { | ||
compatible = "aspeed,ast2500-lpc", "simple-mfd"; | ||
reg = <0x1e789000 0x1000>; | ||
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#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges = <0x0 0x1e789000 0x1000>; | ||
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lpc_bmc: lpc-bmc@0 { | ||
compatible = "aspeed,ast2500-lpc-bmc"; | ||
reg = <0x0 0x80>; | ||
}; | ||
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lpc_host: lpc-host@80 { | ||
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; | ||
reg = <0x80 0x1e0>; | ||
reg-io-width = <4>; | ||
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#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges = <0x0 0x80 0x1e0>; | ||
}; | ||
}; | ||
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Host Node Children | ||
================== | ||
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LPC Host Controller | ||
------------------- | ||
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The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour | ||
between the host and the baseboard management controller. The registers exist | ||
in the "host" portion of the Aspeed LPC controller, which must be the parent of | ||
the LPC host controller node. | ||
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Required properties: | ||
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- compatible: One of: | ||
"aspeed,ast2400-lhc"; | ||
"aspeed,ast2500-lhc"; | ||
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- reg: contains offset/length values of the LHC memory regions. In the | ||
AST2400 and AST2500 there are two regions. | ||
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Example: | ||
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lhc: lhc@20 { | ||
compatible = "aspeed,ast2500-lhc"; | ||
reg = <0x20 0x24 0x48 0x8>; | ||
}; |
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Motorola CPCAP PMIC device tree binding | ||
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Required properties: | ||
- compatible : One or both of "motorola,cpcap" or "ste,6556002" | ||
- reg : SPI chip select | ||
- interrupt-parent : The parent interrupt controller | ||
- interrupts : The interrupt line the device is connected to | ||
- interrupt-controller : Marks the device node as an interrupt controller | ||
- #interrupt-cells : The number of cells to describe an IRQ, should be 2 | ||
- #address-cells : Child device offset number of cells, should be 1 | ||
- #size-cells : Child device size number of cells, should be 0 | ||
- spi-max-frequency : Typically set to 3000000 | ||
- spi-cs-high : SPI chip select direction | ||
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Example: | ||
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&mcspi1 { | ||
cpcap: pmic@0 { | ||
compatible = "motorola,cpcap", "ste,6556002"; | ||
reg = <0>; /* cs0 */ | ||
interrupt-parent = <&gpio1>; | ||
interrupts = <7 IRQ_TYPE_EDGE_RISING>; | ||
interrupt-controller; | ||
#interrupt-cells = <2>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
spi-max-frequency = <3000000>; | ||
spi-cs-high; | ||
}; | ||
}; | ||
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@@ -8476,6 +8476,7 @@ S: Supported | |
F: Documentation/devicetree/bindings/mfd/ | ||
F: drivers/mfd/ | ||
F: include/linux/mfd/ | ||
F: include/dt-bindings/mfd/ | ||
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MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM | ||
M: Ulf Hansson <[email protected]> | ||
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