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x86: apollo_lake: changes GPIO definition in DTS
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This breaks down the GPIO controller definition in DTS into
multiple entries. This allows these controllers to be
referenced by other DTS, and test board overlay files.
And also we can remove the entries in the dts fixup file.

Signed-off-by: Daniel Leung <[email protected]>
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@dcpleung @carlescufi
dcpleung authored and carlescufi committed Feb 5, 2020
1 parent 4e05433 commit 07cb01b
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Showing 5 changed files with 207 additions and 61 deletions.
44 changes: 24 additions & 20 deletions drivers/gpio/gpio_intel_apl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@
* as well, but my (admitted cursory) testing disagrees.
*/

BUILD_ASSERT(DT_APL_GPIO_IRQ == 14);
BUILD_ASSERT(DT_INST_0_INTEL_APL_GPIO_IRQ_0 == 14);

#define REG_PAD_BASE_ADDR 0x000C

Expand Down Expand Up @@ -627,12 +627,15 @@ int gpio_intel_apl_init(struct device *dev)
__ASSERT(nr_isr_devs < GPIO_INTEL_APL_NR_SUBDEVS, "too many subdevs");

if (nr_isr_devs == 0) {
IRQ_CONNECT(DT_APL_GPIO_IRQ,
DT_APL_GPIO_IRQ_PRIORITY,
/* Note that all controllers are using the same IRQ line.
* So we can just use the values from the first instance.
*/
IRQ_CONNECT(DT_INST_0_INTEL_APL_GPIO_IRQ_0,
DT_INST_0_INTEL_APL_GPIO_IRQ_0_PRIORITY,
gpio_intel_apl_isr, NULL,
DT_APL_GPIO_IRQ_SENSE);
DT_INST_0_INTEL_APL_GPIO_IRQ_0_SENSE);

irq_enable(DT_APL_GPIO_IRQ);
irq_enable(DT_INST_0_INTEL_APL_GPIO_IRQ_0);
}

isr_devs[nr_isr_devs++] = dev;
Expand All @@ -647,18 +650,19 @@ int gpio_intel_apl_init(struct device *dev)
return 0;
}

#define GPIO_INTEL_APL_DEV_CFG_DATA(dir_l, dir_u, pos, offset, pins) \
#define GPIO_INTEL_APL_DEV_CFG_DATA(dir_l, dir_u, pos) \
static const struct gpio_intel_apl_config \
gpio_intel_apl_cfg_##dir_l##_##pos = { \
.reg_base = DT_APL_GPIO_BASE_ADDRESS_##dir_u, \
.pin_offset = offset, \
.num_pins = pins, \
.reg_base = (DT_ALIAS_GPIO_##dir_u##_##pos##_BASE_ADDRESS \
& 0xFFFFFF00), \
.pin_offset = DT_ALIAS_GPIO_##dir_u##_##pos##_PIN_OFFSET, \
.num_pins = DT_ALIAS_GPIO_##dir_u##_##pos##_NGPIOS, \
}; \
\
static struct gpio_intel_apl_data gpio_intel_apl_data_##dir_l##_##pos; \
\
DEVICE_AND_API_INIT(gpio_intel_apl_##dir_l##_##pos, \
DT_APL_GPIO_LABEL_##dir_u##_##pos, \
DT_ALIAS_GPIO_##dir_u##_##pos##_LABEL, \
gpio_intel_apl_init, \
&gpio_intel_apl_data_##dir_l##_##pos, \
&gpio_intel_apl_cfg_##dir_l##_##pos, \
Expand All @@ -667,16 +671,16 @@ DEVICE_AND_API_INIT(gpio_intel_apl_##dir_l##_##pos, \

/* "sub" devices. no more than GPIO_INTEL_APL_NR_SUBDEVS of these! */

GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 1, 32, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 2, 32, 14);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 032);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 064);

GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 1, 32, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 2, 32, 13);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 032);
GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 064);

GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 1, 32, 15);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 032);

GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 1, 32, 11);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 000);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 032);
8 changes: 8 additions & 0 deletions dts/bindings/gpio/intel,apl-gpio.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,14 @@ properties:
interrupts:
required: true

ngpios:
required: true

pin-offset:
type: int
required: true
description: Pin offset of this GPIO entry

"#gpio-cells":
const: 2

Expand Down
172 changes: 165 additions & 7 deletions dts/x86/apollo_lake.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,19 @@
#interrupt-cells = <3>;
};

aliases {
gpio-n-000 = &gpio_n_000_031;
gpio-n-032 = &gpio_n_032_063;
gpio-n-064 = &gpio_n_064_077;
gpio-nw-000 = &gpio_nw_000_031;
gpio-nw-032 = &gpio_nw_032_063;
gpio-nw-064 = &gpio_nw_064_076;
gpio-w-000 = &gpio_w_000_031;
gpio-w-032 = &gpio_w_032_046;
gpio-sw-000 = &gpio_sw_000_031;
gpio-sw-032 = &gpio_sw_032_042;
};

soc {
#address-cells = <1>;
#size-cells = <1>;
Expand Down Expand Up @@ -212,19 +225,164 @@
status = "okay";
};

gpio: gpio@d0c50000 {
gpio_n_000_031: gpio@d0c50000 {
compatible = "intel,apl-gpio";
reg = <0xd0c50000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_N_000";
gpio-controller;
#gpio-cells = <2>;

ngpios = <32>;
pin-offset = <0>;

status = "okay";
};

gpio_n_032_063: gpio@d0c50001 {
compatible = "intel,apl-gpio";
reg = <0xd0c50001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_N_032";
gpio-controller;
#gpio-cells = <2>;

ngpios = <32>;
pin-offset = <32>;

status = "okay";
};

gpio_n_064_077: gpio@d0c50002 {
compatible = "intel,apl-gpio";
reg = <0xd0c50002 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_N_064";
gpio-controller;
#gpio-cells = <2>;

ngpios = <14>;
pin-offset = <64>;

status = "okay";
};

gpio_nw_000_031: gpio@d0c40000 {
compatible = "intel,apl-gpio";
reg = <0xd0c40000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_NW_000";
gpio-controller;
#gpio-cells = <2>;

ngpios = <32>;
pin-offset = <0>;

status = "okay";
};

gpio_nw_032_063: gpio@d0c40001 {
compatible = "intel,apl-gpio";
reg = <0xd0c40001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_NW_032";
gpio-controller;
#gpio-cells = <2>;

ngpios = <32>;
pin-offset = <32>;

status = "okay";
};

gpio_nw_064_076: gpio@d0c40002 {
compatible = "intel,apl-gpio";
reg = <0xd0c40002 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_NW_064";
gpio-controller;
#gpio-cells = <2>;

ngpios = <64>;
pin-offset = <13>;

status = "okay";
};

gpio_w_000_031: gpio@d0c70000 {
compatible = "intel,apl-gpio";
reg = <0xd0c50000 0x1000>,
<0xd0c40000 0x1000>,
<0xd0c70000 0x1000>,
<0xd0c00000 0x1000>;
reg = <0xd0c70000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "APL_GPIO";
gpio-controller ;
label = "GPIO_W_000";
gpio-controller;
#gpio-cells = <2>;

ngpios = <32>;
pin-offset = <0>;

status = "okay";
};

gpio_w_032_046: gpio@d0c70001 {
compatible = "intel,apl-gpio";
reg = <0xd0c70001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_W_032";
gpio-controller;
#gpio-cells = <2>;

ngpios = <15>;
pin-offset = <32>;

status = "okay";
};

gpio_sw_000_031: gpio@d0c00000 {
compatible = "intel,apl-gpio";
reg = <0xd0c00000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_SW_000";
gpio-controller;
#gpio-cells = <2>;

ngpios = <32>;
pin-offset = <0>;

status = "okay";
};


gpio_sw_032_042: gpio@d0c00001 {
compatible = "intel,apl-gpio";
reg = <0xd0c00001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;

label = "GPIO_SW_032";
gpio-controller;
#gpio-cells = <2>;

ngpios = <11>;
pin-offset = <32>;

status = "okay";
};

Expand Down
24 changes: 0 additions & 24 deletions soc/x86/apollo_lake/dts_fixup.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,30 +12,6 @@
#define DT_ROM_SIZE CONFIG_FLASH_SIZE

#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define DT_APL_GPIO_BASE_ADDRESS_N DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define DT_APL_GPIO_BASE_ADDRESS_NW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define DT_APL_GPIO_BASE_ADDRESS_W DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define DT_APL_GPIO_BASE_ADDRESS_SW DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3

#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE

#define DT_APL_GPIO_MEM_SIZE_N DT_INTEL_APL_GPIO_D0C50000_SIZE_0
#define DT_APL_GPIO_MEM_SIZE_NW DT_INTEL_APL_GPIO_D0C50000_SIZE_1
#define DT_APL_GPIO_MEM_SIZE_W DT_INTEL_APL_GPIO_D0C50000_SIZE_2
#define DT_APL_GPIO_MEM_SIZE_SW DT_INTEL_APL_GPIO_D0C50000_SIZE_3

#define DT_APL_GPIO_LABEL_N_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_0"
#define DT_APL_GPIO_LABEL_N_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_1"
#define DT_APL_GPIO_LABEL_N_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_2"
#define DT_APL_GPIO_LABEL_NW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_0"
#define DT_APL_GPIO_LABEL_NW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_1"
#define DT_APL_GPIO_LABEL_NW_2 DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_2"
#define DT_APL_GPIO_LABEL_W_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_0"
#define DT_APL_GPIO_LABEL_W_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_1"
#define DT_APL_GPIO_LABEL_SW_0 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_0"
#define DT_APL_GPIO_LABEL_SW_1 DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_1"

#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_INST_0_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_SIZE DT_INST_0_NS16550_SIZE
Expand Down
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