soc: arm: atmel: Add samv71 mcu

Add samv71 related soc files.

Signed-off-by: Gerson Fernando Budke <[email protected]>

soc/arm/atmel_sam/samv71/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  soc_config.c
+  )

soc/arm/atmel_sam/samv71/Kconfig.defconfig.series

@@ -0,0 +1,98 @@
+# Atmel SAM V71 MCU series configuration options
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAMV71
+
+config SOC_SERIES
+	default "samv71"
+
+config SOC_PART_NUMBER
+	default "samv71q21" if SOC_PART_NUMBER_SAMV71Q21
+	default "samv71q20" if SOC_PART_NUMBER_SAMV71Q20
+	default "samv71q19" if SOC_PART_NUMBER_SAMV71Q19
+	default "samv71n21" if SOC_PART_NUMBER_SAMV71N21
+	default "samv71n20" if SOC_PART_NUMBER_SAMV71N20
+	default "samv71n19" if SOC_PART_NUMBER_SAMV71N19
+	default "samv71j21" if SOC_PART_NUMBER_SAMV71J21
+	default "samv71j20" if SOC_PART_NUMBER_SAMV71J20
+	default "samv71j19" if SOC_PART_NUMBER_SAMV71J19
+	default "samv71q21b" if SOC_PART_NUMBER_SAMV71Q21B
+	default "samv71q20b" if SOC_PART_NUMBER_SAMV71Q20B
+	default "samv71q19b" if SOC_PART_NUMBER_SAMV71Q19B
+	default "samv71n21b" if SOC_PART_NUMBER_SAMV71N21B
+	default "samv71n20b" if SOC_PART_NUMBER_SAMV71N20B
+	default "samv71n19b" if SOC_PART_NUMBER_SAMV71N19B
+	default "samv71j21b" if SOC_PART_NUMBER_SAMV71J21B
+	default "samv71j20b" if SOC_PART_NUMBER_SAMV71J20B
+	default "samv71j19b" if SOC_PART_NUMBER_SAMV71J19B
+
+#
+# SAM V71 family has in total 71 peripherals capable of generating interrupts
+# for the revision A and 74 for the revision B (not all Peripheral Identifiers
+# are used).
+#
+config NUM_IRQS
+	default 74 if SOC_ATMEL_SAMV71_REVB
+	default 71
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 300000000
+
+# Configure default device drivers. If a feature is supported by more than one
+# device driver the default configuration will be placed in the board defconfig
+# file.
+
+if DMA
+config DMA_SAM_XDMAC
+	default y
+endif # DMA
+
+if GPIO
+config GPIO_SAM
+	default y
+endif # GPIO
+
+if ADC
+config ADC_SAM_AFEC
+	default y
+endif # ADC
+
+if I2C
+config I2C_SAM_TWIHS
+	default y
+endif # I2C
+
+if I2S
+config I2S_SAM_SSC
+	default y
+endif # I2S
+
+if SPI
+config SPI_SAM
+	default y
+endif # SPI
+
+if USB
+config USB_DC_SAM
+	default y
+endif # USB
+
+if ENTROPY_GENERATOR
+config ENTROPY_SAM_RNG
+	default y
+endif # ENTROPY_GENERATOR
+
+if FLASH
+config SOC_FLASH_SAM
+	default y
+endif # FLASH
+
+if PWM
+config PWM_SAM
+	default y
+endif # PWM
+
+endif # SOC_SERIES_SAMV71

soc/arm/atmel_sam/samv71/Kconfig.series

@@ -0,0 +1,23 @@
+# Atmel SAM V71 MCU series
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAMV71
+	bool "Atmel SAMV71 MCU"
+	select CPU_CORTEX_M7
+	select SOC_FAMILY_SAM
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select CPU_CORTEX_M_HAS_DWT
+	select ASF
+	select XIP
+	select CPU_HAS_ARM_MPU
+	select ARM_MPU
+	select HAS_SWO
+	help
+	  Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers.
+	  Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20,
+	  SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B,
+	  SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B,
+	  SAMV71Q20B, SAMV71Q21B

soc/arm/atmel_sam/samv71/Kconfig.soc

@@ -0,0 +1,168 @@
+# Atmel SAM V71 MCU series
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Atmel SAMV71 MCU Selection"
+	depends on SOC_SERIES_SAMV71
+
+	config SOC_PART_NUMBER_SAMV71Q21
+		bool "SAMV71Q21"
+
+	config SOC_PART_NUMBER_SAMV71Q20
+		bool "SAMV71Q20"
+
+	config SOC_PART_NUMBER_SAMV71Q19
+		bool "SAMV71Q19"
+
+	config SOC_PART_NUMBER_SAMV71N21
+		bool "SAMV71N21"
+
+	config SOC_PART_NUMBER_SAMV71N20
+		bool "SAMV71N20"
+
+	config SOC_PART_NUMBER_SAMV71N19
+		bool "SAMV71N19"
+
+	config SOC_PART_NUMBER_SAMV71J21
+		bool "SAMV71J21"
+
+	config SOC_PART_NUMBER_SAMV71J20
+		bool "SAMV71J20"
+
+	config SOC_PART_NUMBER_SAMV71J19
+		bool "SAMV71J19"
+
+	config SOC_PART_NUMBER_SAMV71Q21B
+		bool "SAMV71Q21B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71Q20B
+		bool "SAMV71Q20B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71Q19B
+		bool "SAMV71Q19B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71N21B
+		bool "SAMV71N21B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71N20B
+		bool "SAMV71N20B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71N19B
+		bool "SAMV71N19B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71J21B
+		bool "SAMV71J21B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71J20B
+		bool "SAMV71J20B"
+		select SOC_ATMEL_SAMV71_REVB
+
+	config SOC_PART_NUMBER_SAMV71J19B
+		bool "SAMV71J19B"
+		select SOC_ATMEL_SAMV71_REVB
+endchoice
+
+if SOC_SERIES_SAMV71
+
+config SOC_ATMEL_SAMV71_REVB
+	bool
+
+config SOC_ATMEL_SAMV71_EXT_SLCK
+	bool "Use external crystal oscillator for slow clock"
+	help
+	  Say y if you want to use external 32 kHz crystal
+	  oscillator to drive the slow clock. Note that this
+	  adds a few seconds to boot time, as the crystal
+	  needs to stabilize after power-up.
+
+	  Says n if you do not need accurate and precise timers.
+	  The slow clock will be driven by the internal fast
+	  RC oscillator running at 32 kHz.
+
+config SOC_ATMEL_SAMV71_EXT_MAINCK
+	bool "Use external crystal oscillator for main clock"
+	help
+	  The main clock is being used to drive the PLL, and
+	  thus driving the processor clock.
+
+	  Say y if you want to use external crystal oscillator
+	  to drive the main clock. Note that this adds about
+	  a second to boot time, as the crystal needs to
+	  stabilize after power-up.
+
+	  The crystal used here can be from 3 to 20 MHz.
+
+	  Says n here will use the internal fast RC oscillator
+	  running at 12 MHz.
+
+config SOC_ATMEL_SAMV71_MDIV
+	int "MDIV"
+	default 2
+	range 1 4
+	help
+	  This divisor defines a ratio between processor clock (HCLK)
+	  and master clock (MCK):
+	  MCK = HCLK / MDIV
+
+config SOC_ATMEL_SAMV71_PLLA_MULA
+	int "PLL MULA"
+	default 24
+	range 1 62
+	help
+	  This is the multiplier MULA used by the PLL.
+	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
+
+	  Board config file can override this settings
+	  for a particular board.
+
+	  Setting MULA=0 would disable PLL at boot, this is currently
+	  not supported.
+
+	  With default of MULA == 24, and DIVA == 1,
+	  PLL is running at 25 times the main clock frequency.
+
+config SOC_ATMEL_SAMV71_PLLA_DIVA
+	int "PLL DIVA"
+	default 1
+	range 1 255
+	help
+	  This is the divider DIVA used by the PLL.
+	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
+
+	  Board config file can override this settings
+	  for a particular board.
+
+	  Setting DIVA=0 would disable PLL at boot, this is currently
+	  not supported.
+
+	  With default of MULA == 24, and DIVA == 1,
+	  PLL is running at 25 times the main clock frequency.
+
+config SOC_ATMEL_SAMV71_WAIT_MODE
+	bool "Go to Wait mode instead of Sleep mode"
+	depends on SOC_ATMEL_SAMV71_EXT_MAINCK
+	default y if DEBUG
+	help
+	  For JTAG debugging CPU clock (HCLK) should not stop. In order
+	  to achieve this, make CPU go to Wait mode instead of Sleep
+	  mode while using external crystal oscillator for main clock.
+
+config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN
+	bool "Disable ERASE pin"
+	help
+	  At reset ERASE pin is configured in System IO mode. Asserting the ERASE
+	  pin at '1' will completely erase Flash memory. Setting this option will
+	  switch the pin to general IO mode giving control of the pin to the GPIO
+	  module.
+
+endif # SOC_SERIES_SAMV71