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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/lin…
…ux/kernel/git/tip/tip Pull irqchip updates from Ingo Molnar: "Various irqchip driver updates, plus a genirq core update that allows the initial spreading of irqs amonst CPUs without having to do it from user-space" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: genirq: Fix null pointer reference in irq_set_affinity_hint() irqchip: gic: Allow interrupt level to be set for PPIs irqchip: mips-gic: Handle pending interrupts once in __gic_irq_dispatch() irqchip: Conexant CX92755 interrupts controller driver irqchip: Devicetree: document Conexant Digicolor irq binding irqchip: omap-intc: Remove unused legacy interface for omap2 irqchip: omap-intc: Fix support for dm814 and dm816 irqchip: mtk-sysirq: Get irq number from register resource size irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support genirq: Set initial affinity in irq_set_affinity_hint()
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Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt
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Conexant Digicolor Interrupt Controller | ||
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Required properties: | ||
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- compatible : should be "cnxt,cx92755-ic" | ||
- reg : Specifies base physical address and size of the interrupt controller | ||
registers (IC) area | ||
- interrupt-controller : Identifies the node as an interrupt controller | ||
- #interrupt-cells : Specifies the number of cells needed to encode an | ||
interrupt source. The value shall be 1. | ||
- syscon: A phandle to the syscon node describing UC registers | ||
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Example: | ||
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intc: interrupt-controller@f0000040 { | ||
compatible = "cnxt,cx92755-ic"; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
reg = <0xf0000040 0x40>; | ||
syscon = <&uc_regs>; | ||
}; |
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Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt
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Omap2/3 intc controller | ||
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On TI omap2 and 3 the intc interrupt controller can provide | ||
96 or 128 IRQ signals to the ARM host depending on the SoC. | ||
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Required Properties: | ||
- compatible: should be one of | ||
"ti,omap2-intc" | ||
"ti,omap3-intc" | ||
"ti,dm814-intc" | ||
"ti,dm816-intc" | ||
"ti,am33xx-intc" | ||
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- interrupt-controller : Identifies the node as an interrupt controller | ||
- #interrupt-cells : Specifies the number of cells needed to encode interrupt | ||
source, should be 1 for intc | ||
- interrupts: interrupt reference to primary interrupt controller | ||
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Please refer to interrupts.txt in this directory for details of the common | ||
Interrupt Controllers bindings used by client devices. | ||
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Example: | ||
intc: interrupt-controller@48200000 { | ||
compatible = "ti,omap3-intc"; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
reg = <0x48200000 0x1000>; | ||
}; |
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/* | ||
* Conexant Digicolor SoCs IRQ chip driver | ||
* | ||
* Author: Baruch Siach <[email protected]> | ||
* | ||
* Copyright (C) 2014 Paradox Innovation Ltd. | ||
* | ||
* This file is licensed under the terms of the GNU General Public | ||
* License version 2. This program is licensed "as is" without any | ||
* warranty of any kind, whether express or implied. | ||
*/ | ||
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#include <linux/io.h> | ||
#include <linux/irq.h> | ||
#include <linux/of.h> | ||
#include <linux/of_address.h> | ||
#include <linux/of_irq.h> | ||
#include <linux/mfd/syscon.h> | ||
#include <linux/regmap.h> | ||
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#include <asm/exception.h> | ||
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#include "irqchip.h" | ||
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#define UC_IRQ_CONTROL 0x04 | ||
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#define IC_FLAG_CLEAR_LO 0x00 | ||
#define IC_FLAG_CLEAR_XLO 0x04 | ||
#define IC_INT0ENABLE_LO 0x10 | ||
#define IC_INT0ENABLE_XLO 0x14 | ||
#define IC_INT0STATUS_LO 0x18 | ||
#define IC_INT0STATUS_XLO 0x1c | ||
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static struct irq_domain *digicolor_irq_domain; | ||
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static void __exception_irq_entry digicolor_handle_irq(struct pt_regs *regs) | ||
{ | ||
struct irq_domain_chip_generic *dgc = digicolor_irq_domain->gc; | ||
struct irq_chip_generic *gc = dgc->gc[0]; | ||
u32 status, hwirq; | ||
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do { | ||
status = irq_reg_readl(gc, IC_INT0STATUS_LO); | ||
if (status) { | ||
hwirq = ffs(status) - 1; | ||
} else { | ||
status = irq_reg_readl(gc, IC_INT0STATUS_XLO); | ||
if (status) | ||
hwirq = ffs(status) - 1 + 32; | ||
else | ||
return; | ||
} | ||
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handle_domain_irq(digicolor_irq_domain, hwirq, regs); | ||
} while (1); | ||
} | ||
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static void digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, | ||
unsigned en_reg, unsigned ack_reg) | ||
{ | ||
struct irq_chip_generic *gc; | ||
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gc = irq_get_domain_generic_chip(digicolor_irq_domain, irq_base); | ||
gc->reg_base = reg_base; | ||
gc->chip_types[0].regs.ack = ack_reg; | ||
gc->chip_types[0].regs.mask = en_reg; | ||
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | ||
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | ||
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | ||
} | ||
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static int __init digicolor_of_init(struct device_node *node, | ||
struct device_node *parent) | ||
{ | ||
static void __iomem *reg_base; | ||
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | ||
struct regmap *ucregs; | ||
int ret; | ||
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reg_base = of_iomap(node, 0); | ||
if (!reg_base) { | ||
pr_err("%s: unable to map IC registers\n", node->full_name); | ||
return -ENXIO; | ||
} | ||
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/* disable all interrupts */ | ||
writel(0, reg_base + IC_INT0ENABLE_LO); | ||
writel(0, reg_base + IC_INT0ENABLE_XLO); | ||
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ucregs = syscon_regmap_lookup_by_phandle(node, "syscon"); | ||
if (IS_ERR(ucregs)) { | ||
pr_err("%s: unable to map UC registers\n", node->full_name); | ||
return PTR_ERR(ucregs); | ||
} | ||
/* channel 1, regular IRQs */ | ||
regmap_write(ucregs, UC_IRQ_CONTROL, 1); | ||
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digicolor_irq_domain = | ||
irq_domain_add_linear(node, 64, &irq_generic_chip_ops, NULL); | ||
if (!digicolor_irq_domain) { | ||
pr_err("%s: unable to create IRQ domain\n", node->full_name); | ||
return -ENOMEM; | ||
} | ||
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ret = irq_alloc_domain_generic_chips(digicolor_irq_domain, 32, 1, | ||
"digicolor_irq", handle_level_irq, | ||
clr, 0, 0); | ||
if (ret) { | ||
pr_err("%s: unable to allocate IRQ gc\n", node->full_name); | ||
return ret; | ||
} | ||
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digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); | ||
digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); | ||
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set_handle_irq(digicolor_handle_irq); | ||
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return 0; | ||
} | ||
IRQCHIP_DECLARE(conexant_digicolor_ic, "cnxt,cx92755-ic", digicolor_of_init); |
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