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A repository of VHDL code from the EES270 Digital Circuits Laboratory course at SIIT, including implementations and simulations for various digital circuits designed during lab sessions.

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npwitk/EES270-Digital-Circuits-Laboratory-VHDL

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EES270 Digital Circuits Laboratory Repository

Warning

.vhd files may not open directly in Logic Works 5. However, you can view all the code in this repository and adapt it to your VHDL files manually if needed.

This repository contains VHDL code developed for lab sessions in the EES270 course at SIIT. The labs focus on designing and simulating digital circuits, including basic combinational circuits, sequential circuits, and more complex designs implemented using Logic Works 5.

File Descriptions

Below is a brief description of each file included in this repository:

Lab 04

  • Lab04_HalfAdder.vhd — A half-adder circuit for binary addition of two single-bit numbers.
  • Lab04_FullAdder.vhd — A full-adder circuit for binary addition, incorporating carry-in and carry-out.

Lab 05

  • Lab05_3Bit_7Seg.vhd — A 3-bit input to 7-segment display design that displays numbers 0 to 7 based on the binary input.

Lab 06

  • Lab06_D_FlipFlop.vhd — Design of a 3-bit up/down counter using D Flip-Flop.
  • Lab06_JK_FlipFlop.vhd — Design of a 3-bit up/down counter using J-K Flip-Flop.

Lab 07

  • Lab07_1_D_FlipFlop.vhd — Design of a 3-bit running LED using D Flip-Flop.
  • Lab07_2_D_FlipFlop.vhd — Enhanced design of a 3-bit running LED using D Flip-Flop, with additional logic for handling unspecified states (selectable to any state).

Lab 08

  • Lab08_Mod4.vhd — Design of a Finite State Machine using D Flip-Flops to perform a mod-4 counting operation.

    This lab does not require a VHDL code implementation but focuses on implementing the design on a DT-1 trainer board. However, implementing this on a real board can be complicated. This code is provided to demonstrate how the logic works.

Lab 09

  • Lab09_VM.vhd — Design of a vending machine

Tools Used

  • Logic Works 5: Used for testing and simulation of PLD designs.
  • VHDL: Hardware description language for digital circuit design.

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A repository of VHDL code from the EES270 Digital Circuits Laboratory course at SIIT, including implementations and simulations for various digital circuits designed during lab sessions.

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