Restrict register allocation to XMM0-15

oldcwj · Sep 22, 2022 · 71e2ede · 71e2ede
1 parent ca14d90
commit 71e2ede
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/...vm.core.graal.amd64/src/com/oracle/svm/core/graal/amd64/SubstrateAMD64RegisterConfig.java b/...vm.core.graal.amd64/src/com/oracle/svm/core/graal/amd64/SubstrateAMD64RegisterConfig.java
@@ -45,7 +45,6 @@
 import static jdk.vm.ci.amd64.AMD64.rdi;
 import static jdk.vm.ci.amd64.AMD64.rdx;
 import static jdk.vm.ci.amd64.AMD64.rsi;
-import static jdk.vm.ci.amd64.AMD64.valueRegistersAVX512;
 import static jdk.vm.ci.amd64.AMD64.valueRegistersSSE;
 import static jdk.vm.ci.amd64.AMD64.xmm0;
 import static jdk.vm.ci.amd64.AMD64.xmm1;
@@ -118,7 +117,13 @@ public SubstrateAMD64RegisterConfig(ConfigKind config, MetaAccessProvider metaAc
         boolean haveAVX512 = ((AMD64) target.arch).getFeatures().contains(AMD64.CPUFeature.AVX512F);
         ArrayList<Register> regs;
         if (haveAVX512) {
-            regs = new ArrayList<>(valueRegistersAVX512.asList());
+            /*
+             * GR-40969: We would like to use valueRegistersAVX512. However, we emit a mix of VEX
+             * and EVEX encoded instructions, and the VEX variants cannot address the extended
+             * AVX-512 registers (XMM16-31). For now, limit ourselves to XMM0-15.
+             */
+            regs = new ArrayList<>(valueRegistersSSE.asList());
+            regs.addAll(MASK_REGISTERS.asList());
         } else {
             regs = new ArrayList<>(valueRegistersSSE.asList());
             if (SubstrateUtil.HOSTED && AMD64CalleeSavedRegisters.isRuntimeCompilationEnabled()) {