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ARM: mvebu: support running big-endian
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Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.

Signed-off-by: Ben Dooks <[email protected]>
Tested-by: Thomas Petazzoni <[email protected]>
Acked-by: Jason Cooper <[email protected]>
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bjdooks-ct committed Oct 19, 2013
1 parent 50eec2f commit bca028e
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Showing 3 changed files with 8 additions and 0 deletions.
1 change: 1 addition & 0 deletions arch/arm/mach-mvebu/Kconfig
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
config ARCH_MVEBU
bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_CLOCKEVENTS
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3 changes: 3 additions & 0 deletions arch/arm/mach-mvebu/coherency_ll.S
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Expand Up @@ -20,6 +20,8 @@
#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4

#include <asm/assembler.h>

.text
/*
* r0: Coherency fabric base register address
Expand All @@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent)
/* Create bit by cpu index */
mov r3, #(1 << 24)
lsl r1, r3, r1
ARM_BE8(rev r1, r1)

/* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
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4 changes: 4 additions & 0 deletions arch/arm/mach-mvebu/headsmp.S
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Expand Up @@ -21,12 +21,16 @@
#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/assembler.h>

/*
* Armada XP specific entry point for secondary CPUs.
* We add the CPU to the coherency fabric and then jump to secondary
* startup
*/
ENTRY(armada_xp_secondary_startup)
ARM_BE8(setend be ) @ go BE8 if entered LE

/* Get coherency fabric base physical address */
adr r0, 1f
ldr r1, [r0]
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