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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/gerg/m68knommu Pull m68knommu updates from Greg Ungerer: "The bulk of the changes are generalizing the ColdFire v3 core support and adding in 537x CPU support. Also a couple of other bug fixes, one to fix a reintroduction of a past bug in the romfs filesystem nommu support." * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68knommu: enable Timer on coldfire 532x m68knommu: fix ColdFire 5373/5329 QSPI base address m68knommu: add support for configuring a Freescale M5373EVB board m68knommu: add support for the ColdFire 537x family of CPUs m68knommu: make ColdFire M532x platform support more v3 generic m68knommu: create and use a common M53xx ColdFire class of CPUs m68k: remove unused asm/dbg.h m68k: Set ColdFire ACR1 cache mode depending on kernel configuration romfs: fix nommu map length to keep inside filesystem m68k: clean up unused "config ROMVECSIZE"
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Original file line number | Diff line number | Diff line change |
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@@ -1,7 +1,7 @@ | ||
/***************************************************************************/ | ||
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/* | ||
* linux/arch/m68knommu/platform/532x/config.c | ||
* m53xx.c -- platform support for ColdFire 53xx based boards | ||
* | ||
* Copyright (C) 1999-2002, Greg Ungerer ([email protected]) | ||
* Copyright (C) 2000, Lineo (www.lineo.com) | ||
|
@@ -118,7 +118,8 @@ static struct clk * const enable_clks[] __initconst = { | |
&__clk_0_24, /* mcfuart.0 */ | ||
&__clk_0_25, /* mcfuart.1 */ | ||
&__clk_0_26, /* mcfuart.2 */ | ||
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&__clk_0_28, /* mcftmr.0 */ | ||
&__clk_0_29, /* mcftmr.1 */ | ||
&__clk_0_32, /* mcfpit.0 */ | ||
&__clk_0_33, /* mcfpit.1 */ | ||
&__clk_0_37, /* mcfeport.0 */ | ||
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@@ -134,8 +135,6 @@ static struct clk * const disable_clks[] __initconst = { | |
&__clk_0_17, /* edma */ | ||
&__clk_0_22, /* mcfi2c.0 */ | ||
&__clk_0_23, /* mcfqspi.0 */ | ||
&__clk_0_28, /* mcftmr.0 */ | ||
&__clk_0_29, /* mcftmr.1 */ | ||
&__clk_0_30, /* mcftmr.2 */ | ||
&__clk_0_31, /* mcftmr.3 */ | ||
&__clk_0_34, /* mcfpit.2 */ | ||
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@@ -153,7 +152,7 @@ static struct clk * const disable_clks[] __initconst = { | |
}; | ||
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static void __init m532x_clk_init(void) | ||
static void __init m53xx_clk_init(void) | ||
{ | ||
unsigned i; | ||
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@@ -169,7 +168,7 @@ static void __init m532x_clk_init(void) | |
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) | ||
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static void __init m532x_qspi_init(void) | ||
static void __init m53xx_qspi_init(void) | ||
{ | ||
/* setup QSPS pins for QSPI with gpio CS control */ | ||
writew(0x01f0, MCFGPIO_PAR_QSPI); | ||
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@@ -179,15 +178,15 @@ static void __init m532x_qspi_init(void) | |
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/***************************************************************************/ | ||
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static void __init m532x_uarts_init(void) | ||
static void __init m53xx_uarts_init(void) | ||
{ | ||
/* UART GPIO initialization */ | ||
writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART); | ||
} | ||
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/***************************************************************************/ | ||
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static void __init m532x_fec_init(void) | ||
static void __init m53xx_fec_init(void) | ||
{ | ||
u8 v; | ||
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@@ -217,11 +216,11 @@ void __init config_BSP(char *commandp, int size) | |
} | ||
#endif | ||
mach_sched_init = hw_timer_init; | ||
m532x_clk_init(); | ||
m532x_uarts_init(); | ||
m532x_fec_init(); | ||
m53xx_clk_init(); | ||
m53xx_uarts_init(); | ||
m53xx_fec_init(); | ||
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) | ||
m532x_qspi_init(); | ||
m53xx_qspi_init(); | ||
#endif | ||
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#ifdef CONFIG_BDM_DISABLE | ||
|
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