Skip to content

Commit

Permalink
Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/ker…
Browse files Browse the repository at this point in the history
…nel/git/wsa/linux

Pull i2c updates from Wolfram Sang:
 "Here is the pull request from the i2c subsystem.  It got a little
  delayed because I needed to wait for a dependency to be included
  (commit b424080: "reset: Add optional resets and stubs").  Plus,
  I had some email problems.  All done now, the highlights are:

   - drivers can now deprecate their use of i2c classes.  That shouldn't
     be used on embedded platforms anyhow and was often blindly
     copy&pasted.  This mechanism gives users time to switch away and
     ultimately boot faster once the use of classes for those drivers is
     gone for good.

   - new drivers for QUP, Cadence, efm32

   - tracepoint support for I2C and SMBus

   - bigger cleanups for the mv64xxx, nomadik, and designware drivers

  And the usual bugfixes, cleanups, feature additions.  Most stuff has
  been in linux-next for a while.  Just some hot fixes and new drivers
  were added a bit more recently."

* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (63 commits)
  i2c: cadence: fix Kconfig dependency
  i2c: Add driver for Cadence I2C controller
  i2c: cadence: Document device tree bindings
  Documentation: i2c: improve section about flags mangling the protocol
  i2c: qup: use proper type fro clk_freq
  i2c: qup: off by ones in qup_i2c_probe()
  i2c: efm32: fix binding doc
  MAINTAINERS: update I2C web resources
  i2c: qup: New bus driver for the Qualcomm QUP I2C controller
  i2c: qup: Add device tree bindings information
  i2c: i2c-xiic: deprecate class based instantiation
  i2c: i2c-sirf: deprecate class based instantiation
  i2c: i2c-mv64xxx: deprecate class based instantiation
  i2c: i2c-designware-platdrv: deprecate class based instantiation
  i2c: i2c-davinci: deprecate class based instantiation
  i2c: i2c-bcm2835: deprecate class based instantiation
  i2c: mv64xxx: Fix reset controller handling
  i2c: omap: fix usage of IS_ERR_VALUE with pm_runtime_get_sync
  i2c: efm32: new bus driver
  i2c: exynos5: remove unnecessary cast of void pointer
  ...
torvalds committed Apr 9, 2014
2 parents 97e18dc + 1fbeab0 commit 39de65a
Showing 64 changed files with 3,292 additions and 501 deletions.
2 changes: 2 additions & 0 deletions Documentation/devicetree/bindings/i2c/i2c-at91.txt
Original file line number Diff line number Diff line change
@@ -12,6 +12,7 @@ Required properties :
- clocks: phandles to input clocks.

Optional properties:
- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
- Child nodes conforming to i2c bus binding

Examples :
@@ -23,6 +24,7 @@ i2c0: i2c@fff84000 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clock-frequency = <400000>;

24c512@50 {
compatible = "24c512";
24 changes: 24 additions & 0 deletions Documentation/devicetree/bindings/i2c/i2c-cadence.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
Binding for the Cadence I2C controller

Required properties:
- reg: Physical base address and size of the controller's register area.
- compatible: Compatibility string. Must be 'cdns,i2c-r1p10'.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt bindings.
- #address-cells: Should be 1.
- #size-cells: Should be 0.

Optional properties:
- clock-frequency: Desired operating frequency, in Hz, of the bus.
- clock-names: Input clock name, should be 'pclk'.

Example:
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
clocks = <&clkc 38>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xe0004000 0x1000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
8 changes: 8 additions & 0 deletions Documentation/devicetree/bindings/i2c/i2c-designware.txt
Original file line number Diff line number Diff line change
@@ -14,6 +14,12 @@ Optional properties :
- i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
This option is only supported in hardware blocks version 1.11a or newer.

- i2c-scl-falling-time : should contain the SCL falling time in nanoseconds.
This value which is by default 300ns is used to compute the tLOW period.

- i2c-sda-falling-time : should contain the SDA falling time in nanoseconds.
This value which is by default 300ns is used to compute the tHIGH period.

Example :

i2c@f0000 {
@@ -34,4 +40,6 @@ Example :
interrupts = <12 1>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <300>;
i2c-scl-falling-time-ns = <300>;
};
34 changes: 34 additions & 0 deletions Documentation/devicetree/bindings/i2c/i2c-efm32.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
* Energymicro efm32 i2c controller

Required properties :

- reg : Offset and length of the register set for the device
- compatible : should be "energymicro,efm32-i2c"
- interrupts : the interrupt number
- clocks : reference to the module clock

Recommended properties :

- clock-frequency : maximal I2C bus clock frequency in Hz.
- efm32,location : Decides the location of the USART I/O pins.
Allowed range : [0 .. 6]

Example:
i2c0: i2c@4000a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "energymicro,efm32-i2c";
reg = <0x4000a000 0x400>;
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
status = "ok";
efm32,location = <3>;

eeprom@50 {
compatible = "microchip,24c02";
reg = <0x50>;
pagesize = <16>;
};
};

20 changes: 14 additions & 6 deletions Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
Original file line number Diff line number Diff line change
@@ -4,19 +4,27 @@
Required properties :

- reg : Offset and length of the register set for the device
- compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
or "marvell,mv78230-i2c" or "marvell,mv78230-a0-i2c"
Note: Only use "marvell,mv78230-a0-i2c" for a very rare,
initial version of the SoC which had broken offload
support. Linux auto-detects this and sets it
appropriately.
- compatible : Should be either:
- "allwinner,sun4i-i2c"
- "allwinner,sun6i-a31-i2c"
- "marvell,mv64xxx-i2c"
- "marvell,mv78230-i2c"
- "marvell,mv78230-a0-i2c"
* Note: Only use "marvell,mv78230-a0-i2c" for a
very rare, initial version of the SoC which
had broken offload support. Linux
auto-detects this and sets it appropriately.
- interrupts : The interrupt number

Optional properties :

- clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
default frequency is 100kHz

- resets : phandle to the parent reset controller. Mandatory
whenever you're using the "allwinner,sun6i-a31-i2c"
compatible.

Examples:

i2c@11000 {
14 changes: 10 additions & 4 deletions Documentation/devicetree/bindings/i2c/i2c-rcar.txt
Original file line number Diff line number Diff line change
@@ -6,18 +6,24 @@ Required properties:
"renesas,i2c-r8a7778"
"renesas,i2c-r8a7779"
"renesas,i2c-r8a7790"
"renesas,i2c-r8a7791"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt specifier.

Optional properties:
- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this
propoerty indicates the default frequency 100 kHz.
- clocks: clock specifier.

Examples :

i2c0: i2c@e6500000 {
compatible = "renesas,i2c-rcar-h2";
reg = <0 0xe6500000 0 0x428>;
interrupts = <0 174 0x4>;
i2c0: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7791";
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
clock-frequency = <400000>;
};
40 changes: 40 additions & 0 deletions Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
Qualcomm Universal Peripheral (QUP) I2C controller

Required properties:
- compatible: Should be:
* "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064.
* "qcom,i2c-qup-v2.1.1" for 8974 v1.
* "qcom,i2c-qup-v2.2.1" for 8974 v2 and later.
- reg: Should contain QUP register address and length.
- interrupts: Should contain I2C interrupt.

- clocks: A list of phandles + clock-specifiers, one for each entry in
clock-names.
- clock-names: Should contain:
* "core" for the core clock
* "iface" for the AHB clock

- #address-cells: Should be <1> Address cells for i2c device address
- #size-cells: Should be <0> as i2c addresses have no size component

Optional properties:
- clock-frequency: Should specify the desired i2c bus clock frequency in Hz,
defaults to 100kHz if omitted.

Child nodes should conform to i2c bus binding.

Example:

i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x1000>;
interrupts = <0 96 0>;

clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

clock-frequency = <355000>;

#address-cells = <1>;
#size-cells = <0>;
};
1 change: 1 addition & 0 deletions Documentation/i2c/busses/i2c-i801
Original file line number Diff line number Diff line change
@@ -26,6 +26,7 @@ Supported adapters:
* Intel Wellsburg (PCH)
* Intel Coleto Creek (PCH)
* Intel Wildcat Point-LP (PCH)
* Intel BayTrail (SOC)
Datasheets: Publicly available at the Intel website

On Intel Patsburg and later chipsets, both the normal host SMBus controller
2 changes: 1 addition & 1 deletion Documentation/i2c/functionality
Original file line number Diff line number Diff line change
@@ -46,7 +46,7 @@ A few combinations of the above flags are also defined for your convenience:
and write_block_data commands
I2C_FUNC_SMBUS_I2C_BLOCK Handles the SMBus read_i2c_block_data
and write_i2c_block_data commands
I2C_FUNC_SMBUS_EMUL Handles all SMBus commands than can be
I2C_FUNC_SMBUS_EMUL Handles all SMBus commands that can be
emulated by a real I2C adapter (using
the transparent emulation layer)

35 changes: 20 additions & 15 deletions Documentation/i2c/i2c-protocol
Original file line number Diff line number Diff line change
@@ -6,8 +6,8 @@ Key to symbols
S (1 bit) : Start bit
P (1 bit) : Stop bit
Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit) : Accept and reverse accept bit.
Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
A, NA (1 bit) : Accept and reverse accept bit.
Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
get a 10 bit I2C address.
Comm (8 bits): Command byte, a data byte which often selects a register on
the device.
@@ -49,11 +49,20 @@ a byte read, followed by a byte write:
Modified transactions
=====================

The following modifications to the I2C protocol can also be generated,
with the exception of I2C_M_NOSTART these are usually only needed to
work around device issues:
The following modifications to the I2C protocol can also be generated by
setting these flags for i2c messages. With the exception of I2C_M_NOSTART, they
are usually only needed to work around device issues:

Flag I2C_M_NOSTART:
I2C_M_IGNORE_NAK:
Normally message is interrupted immediately if there is [NA] from the
client. Setting this flag treats any [NA] as [A], and all of
message is sent.
These messages may still fail to SCL lo->hi timeout.

I2C_M_NO_RD_ACK:
In a read message, master A/NA bit is skipped.

I2C_M_NOSTART:
In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
point. For example, setting I2C_M_NOSTART on the second partial message
generates something like:
@@ -67,17 +76,13 @@ work around device issues:
I2C device but may also be used between direction changes by some
rare devices.

Flags I2C_M_REV_DIR_ADDR
I2C_M_REV_DIR_ADDR:
This toggles the Rd/Wr flag. That is, if you want to do a write, but
need to emit an Rd instead of a Wr, or vice versa, you set this
flag. For example:
S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P

Flags I2C_M_IGNORE_NAK
Normally message is interrupted immediately if there is [NA] from the
client. Setting this flag treats any [NA] as [A], and all of
message is sent.
These messages may still fail to SCL lo->hi timeout.

Flags I2C_M_NO_RD_ACK
In a read message, master A/NA bit is skipped.
I2C_M_STOP:
Force a stop condition (P) after the message. Some I2C related protocols
like SCCB require that. Normally, you really don't want to get interrupted
between the messages of one transfer.
4 changes: 3 additions & 1 deletion MAINTAINERS
Original file line number Diff line number Diff line change
@@ -1427,6 +1427,7 @@ F: drivers/cpuidle/cpuidle-zynq.c
N: zynq
N: xilinx
F: drivers/clocksource/cadence_ttc_timer.c
F: drivers/i2c/busses/i2c-cadence.c
F: drivers/mmc/host/sdhci-of-arasan.c

ARM SMMU DRIVER
@@ -4308,7 +4309,8 @@ F: drivers/i2c/i2c-stub.c
I2C SUBSYSTEM
M: Wolfram Sang <[email protected]>
L: [email protected]
W: http://i2c.wiki.kernel.org/
W: https://i2c.wiki.kernel.org/
Q: https://patchwork.ozlabs.org/project/linux-i2c/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
S: Maintained
F: Documentation/i2c/
Loading

0 comments on commit 39de65a

Please sign in to comment.