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    • rv32-tips

      Public
      0000Updated Oct 13, 2020Oct 13, 2020
    • Silicon-validated SoC implementation of the PicoSoc/PicoRV32
      Verilog
      Other
      66000Updated Oct 10, 2020Oct 10, 2020
    • RISC-V Instruction Set Manual
      TeX
      Creative Commons Attribution 4.0 International
      677000Updated Sep 20, 2020Sep 20, 2020
    • Verilog
      0000Updated Sep 18, 2020Sep 18, 2020
    • Shell
      0000Updated Sep 17, 2020Sep 17, 2020
    • openlane

      Public
      OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
      Verilog
      Apache License 2.0
      384000Updated Sep 11, 2020Sep 11, 2020
    • raptor

      Public
      Arm Cortex-M0 based Customizable SoC for IoT Applications
      C
      9000Updated Sep 10, 2020Sep 10, 2020
    • ravenna

      Public
      C
      5000Updated Sep 5, 2020Sep 5, 2020
    • riscv-pk

      Public
      RISC-V Proxy Kernel
      C
      Other
      313000Updated Aug 8, 2020Aug 8, 2020