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Updated Golden logs and QL script.
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@aram-rs
aram-rs committed Jun 10, 2022
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136 changes: 68 additions & 68 deletions .github/logs/Golden_synth_rs_ade_no_bram_no_dsp/3des_vhdl/yosys_output.log
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140 changes: 70 additions & 70 deletions .github/logs/Golden_synth_rs_ade_no_bram_no_dsp/8bit_vedic_multiplier/yosys_output.log
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192 changes: 96 additions & 96 deletions .github/logs/Golden_synth_rs_ade_no_bram_no_dsp/IR_Remote/yosys_output.log
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116 changes: 58 additions & 58 deletions .github/logs/Golden_synth_rs_ade_no_bram_no_dsp/XTEA_Core/yosys_output.log
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98 changes: 49 additions & 49 deletions .github/logs/Golden_synth_rs_ade_no_bram_no_dsp/adc_ctrl/yosys_output.log
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@
| |
\----------------------------------------------------------------------------/

Yosys-Verific 0.0.37
Yosys 0.17+76 (git sha1 2073f9d19, gcc 9.1.0 -fPIC -Os)
Yosys-Verific 0.0.40
Yosys 0.17+76 (git sha1 035496b50, gcc 9.1.0 -fPIC -Os)


-- Executing script file `yosys.ys' --
Expand All @@ -35,7 +35,7 @@ yosys> read -incdir .
yosys> verific -vlog-incdir .

1. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr22_SW_Release, released at Thu Apr 28 20:08:21 2022.
Built with Verific Apr22_SW_Release, released at Thu Apr 28 08:08:21 2022.

yosys> verilog_defaults -add -I.

Expand All @@ -44,7 +44,7 @@ yosys> read -sv prim_mubi_pkg.sv ast_pkg.sv adc_ctrl_reg_pkg.sv prim_alert_pkg.s
yosys> verific -sv prim_mubi_pkg.sv ast_pkg.sv adc_ctrl_reg_pkg.sv prim_alert_pkg.sv prim_pkg.sv prim_secded_pkg.sv top_pkg.sv prim_subreg_pkg.sv tlul_pkg.sv adc_ctrl.sv adc_ctrl_core.sv adc_ctrl_fsm.sv adc_ctrl_intr.sv adc_ctrl_reg_top.sv prim_alert_sender.sv prim_buf.sv prim_generic_buf.sv prim_subreg.sv prim_generic_buf.sv prim_diff_decode.sv prim_flop_2sync.sv prim_generic_flop_2sync.sv prim_generic_flop.sv tlul_cmd_intg_chk.sv prim_secded_inv_64_57_dec.sv tlul_data_integ_dec.sv prim_secded_inv_39_32_dec.sv tlul_rsp_intg_gen.sv prim_secded_inv_64_57_enc.sv tlul_data_integ_enc.sv prim_secded_inv_39_32_enc.sv tlul_adapter_reg.sv tlul_err.sv prim_sync_reqack.sv prim_reg_cdc.sv prim_subreg_ext.sv prim_pulse_sync.sv prim_intr_hw.sv

2. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr22_SW_Release, released at Thu Apr 28 20:08:21 2022.
Built with Verific Apr22_SW_Release, released at Thu Apr 28 08:08:21 2022.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'prim_mubi_pkg.sv'
VERIFIC-WARNING [VERI-2418] prim_mubi_pkg.sv:19: parameter 'MuBi4Width' declared inside package 'prim_mubi_pkg' shall be treated as localparam
VERIFIC-WARNING [VERI-2418] prim_mubi_pkg.sv:148: parameter 'MuBi8Width' declared inside package 'prim_mubi_pkg' shall be treated as localparam
Expand Down Expand Up @@ -210,21 +210,21 @@ VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'prim_intr_hw.sv'

yosys> synth_rs -top adc_ctrl -tech genesis -goal area -de -no_dsp -no_bram -verilog synthesized.v

3. Executing synth_rs pass: v0.4.53
3. Executing synth_rs pass: v0.4.55

yosys> read_verilog -lib -specify -nomem2reg +/rapidsilicon/common/cells_sim.v +/rapidsilicon/genesis/cells_sim.v

3.1. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/common/cells_sim.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation.
3.1. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/common/cells_sim.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/common/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\inv'.
Generating RTLIL representation for module `\buff'.
Generating RTLIL representation for module `\logic_0'.
Generating RTLIL representation for module `\logic_1'.
Generating RTLIL representation for module `\gclkbuff'.
Successfully finished Verilog frontend.

3.2. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/cells_sim.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/cells_sim.v' to AST representation.
3.2. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/cells_sim.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\dffsre'.
Generating RTLIL representation for module `\dffnsre'.
Generating RTLIL representation for module `\latchsre'.
Expand Down Expand Up @@ -2925,8 +2925,8 @@ yosys> techmap -map +/techmap.v -map +/rapidsilicon/genesis/arith_map.v

3.25. Executing TECHMAP pass (map to technology primitives).

3.25.1. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v' to AST representation.
3.25.1. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Expand All @@ -2953,8 +2953,8 @@ Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

3.25.2. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/arith_map.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/arith_map.v' to AST representation.
3.25.2. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/arith_map.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_rs_alu'.
Successfully finished Verilog frontend.

Expand Down Expand Up @@ -2989,7 +2989,7 @@ Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001000 for ce
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011000 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu.
No more expansions possible.
<suppressed ~3408 debug messages>
<suppressed ~3414 debug messages>

yosys> stat

Expand Down Expand Up @@ -3616,8 +3616,8 @@ yosys> techmap -map +/techmap.v

3.31. Executing TECHMAP pass (map to technology primitives).

3.31.1. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v' to AST representation.
3.31.1. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Expand Down Expand Up @@ -5834,27 +5834,27 @@ Optimizing module adc_ctrl.

3.38.23. Finished OPT passes. (There is nothing left to do.)

yosys> abc -script /home/users/temp_dir/yosys_0SZYXz/abc_tmp_1.scr
yosys> abc -script /home/users/temp_dir/yosys_dVmuc9/abc_tmp_1.scr

3.39. Executing ABC pass (technology mapping using ABC).

3.39.1. Extracting gate netlist of module `\adc_ctrl' to `<abc-temp-dir>/input.blif'..
Extracted 2559 gates and 3314 wires to a netlist network with 755 inputs and 682 outputs.

3.39.1.1. Executing ABC.
DE: #PIs = 755 #Luts = 1120 Max Lvl = 12 Avg Lvl = 10.15 [ 0.27 sec. at Pass 0]
DE: #PIs = 755 #Luts = 1033 Max Lvl = 11 Avg Lvl = 9.23 [ 8.02 sec. at Pass 1]
DE: #PIs = 755 #Luts = 1030 Max Lvl = 13 Avg Lvl = 10.18 [ 1.62 sec. at Pass 2]
DE: #PIs = 755 #Luts = 1016 Max Lvl = 11 Avg Lvl = 8.58 [ 3.13 sec. at Pass 3]
DE: #PIs = 755 #Luts = 1016 Max Lvl = 11 Avg Lvl = 8.58 [ 2.48 sec. at Pass 4]
DE: #PIs = 755 #Luts = 1010 Max Lvl = 12 Avg Lvl = 9.38 [ 3.87 sec. at Pass 5]
DE: #PIs = 755 #Luts = 1008 Max Lvl = 13 Avg Lvl = 10.86 [ 2.59 sec. at Pass 6]
DE: #PIs = 755 #Luts = 991 Max Lvl = 11 Avg Lvl = 7.87 [ 4.19 sec. at Pass 7]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 2.21 sec. at Pass 8]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 3.77 sec. at Pass 9]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 2.25 sec. at Pass 10]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 4.05 sec. at Pass 11]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 0.49 sec. at Pass 12]
DE: #PIs = 755 #Luts = 1120 Max Lvl = 12 Avg Lvl = 10.15 [ 0.13 sec. at Pass 0]
DE: #PIs = 755 #Luts = 1033 Max Lvl = 11 Avg Lvl = 9.23 [ 6.34 sec. at Pass 1]
DE: #PIs = 755 #Luts = 1030 Max Lvl = 13 Avg Lvl = 10.18 [ 1.32 sec. at Pass 2]
DE: #PIs = 755 #Luts = 1016 Max Lvl = 11 Avg Lvl = 8.58 [ 2.09 sec. at Pass 3]
DE: #PIs = 755 #Luts = 1016 Max Lvl = 11 Avg Lvl = 8.58 [ 1.68 sec. at Pass 4]
DE: #PIs = 755 #Luts = 1010 Max Lvl = 12 Avg Lvl = 9.38 [ 2.86 sec. at Pass 5]
DE: #PIs = 755 #Luts = 1008 Max Lvl = 13 Avg Lvl = 10.86 [ 1.60 sec. at Pass 6]
DE: #PIs = 755 #Luts = 991 Max Lvl = 11 Avg Lvl = 7.87 [ 2.79 sec. at Pass 7]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 1.58 sec. at Pass 8]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 2.93 sec. at Pass 9]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 1.67 sec. at Pass 10]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 3.60 sec. at Pass 11]
DE: #PIs = 755 #Luts = 987 Max Lvl = 10 Avg Lvl = 7.76 [ 0.31 sec. at Pass 12]

yosys> opt

Expand Down Expand Up @@ -6004,8 +6004,8 @@ yosys> techmap -map +/techmap.v -map +/rapidsilicon/genesis/ffs_map.v

3.46. Executing TECHMAP pass (map to technology primitives).

3.46.1. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v' to AST representation.
3.46.1. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Expand All @@ -6032,8 +6032,8 @@ Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

3.46.2. Executing Verilog-2005 frontend: /home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/ffs_map.v
Parsing Verilog input from `/home/users/aram/Workspace/clean_repo/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/ffs_map.v' to AST representation.
3.46.2. Executing Verilog-2005 frontend: /home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/ffs_map.v
Parsing Verilog input from `/home/users/khyber.runner/yosys_verific_runner/_work/yosys_verific_rs/yosys_verific_rs/yosys/install/bin/../share/yosys/rapidsilicon/genesis/ffs_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Expand Down Expand Up @@ -6233,22 +6233,22 @@ Optimizing module adc_ctrl.

3.53.16. Finished OPT passes. (There is nothing left to do.)

yosys> abc -script /home/users/temp_dir/yosys_0SZYXz/abc_tmp_2.scr
yosys> abc -script /home/users/temp_dir/yosys_dVmuc9/abc_tmp_2.scr

3.54. Executing ABC pass (technology mapping using ABC).

3.54.1. Extracting gate netlist of module `\adc_ctrl' to `<abc-temp-dir>/input.blif'..
Extracted 3205 gates and 3961 wires to a netlist network with 754 inputs and 680 outputs.

3.54.1.1. Executing ABC.
DE: #PIs = 754 #Luts = 1004 Max Lvl = 11 Avg Lvl = 9.19 [ 0.14 sec. at Pass 0]
DE: #PIs = 754 #Luts = 991 Max Lvl = 7 Avg Lvl = 6.19 [ 7.59 sec. at Pass 1]
DE: #PIs = 754 #Luts = 991 Max Lvl = 7 Avg Lvl = 6.19 [ 2.31 sec. at Pass 2]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 3.09 sec. at Pass 3]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 2.13 sec. at Pass 4]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 3.41 sec. at Pass 5]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 1.95 sec. at Pass 6]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 0.52 sec. at Pass 7]
DE: #PIs = 754 #Luts = 1004 Max Lvl = 11 Avg Lvl = 9.19 [ 0.10 sec. at Pass 0]
DE: #PIs = 754 #Luts = 991 Max Lvl = 7 Avg Lvl = 6.19 [ 5.14 sec. at Pass 1]
DE: #PIs = 754 #Luts = 991 Max Lvl = 7 Avg Lvl = 6.19 [ 1.47 sec. at Pass 2]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 2.26 sec. at Pass 3]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 1.56 sec. at Pass 4]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 2.62 sec. at Pass 5]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 1.89 sec. at Pass 6]
DE: #PIs = 754 #Luts = 985 Max Lvl = 11 Avg Lvl = 8.77 [ 0.48 sec. at Pass 7]

yosys> opt

Expand Down Expand Up @@ -6391,9 +6391,9 @@ yosys> clean_zerowidth
Dumping module `\adc_ctrl'.

Warnings: 124 unique messages, 124 total
End of script. Logfile hash: cf8e2ba42c, CPU: user 44.00s system 3.54s, MEM: 93.39 MB peak
Yosys 0.17+76 (git sha1 2073f9d19, gcc 9.1.0 -fPIC -Os)
Time spent: 92% 6x abc (478 sec), 2% 40x opt_dff (13 sec), ...
real 137.64
user 480.20
sys 36.23
End of script. Logfile hash: e157f1f819, CPU: user 32.02s system 1.28s, MEM: 94.95 MB peak
Yosys 0.17+76 (git sha1 035496b50, gcc 9.1.0 -fPIC -Os)
Time spent: 93% 6x abc (363 sec), 2% 40x opt_dff (8 sec), ...
real 99.87
user 366.55
sys 23.86
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