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  • ICer in Southeast University
  • WuHan

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out-of-order55/README.md

My github stats

⚡ 我的技术栈 | My Tech Stack

  • systemverilog verilog chisel c python

  • verilator quartus vivado vcs

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  1. GRVcore Public

    a simple OoO processor

    Scala 1

  2. prefetcher-sim Public

    A sim has l1 and l2 cache

    Python 3

  3. SRT-Divider Public

    简单的未优化的SRT除法器

    Verilog 7

  4. DCache Public

    2 way|PLRU|2*4k

    SystemVerilog 5

  5. cache-sim Public

    一个可配置的cachesim

    C 1

  6. booth-multiplier Public

    基4booth乘法器设计与验证

    VHDL 9

211 contributions in the last year

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Activity overview

Loading A graph representing out-of-order55's contributions from February 11, 2024 to February 17, 2025. The contributions are 99% commits, 1% issues, 0% pull requests, 0% code review.

Contribution activity

February 2025

Created 3 repositories
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