mainboard/intel: add leafhill board directory

This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.

The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.

Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Signed-off-by: Brenton Dong <[email protected]>
Reviewed-on: https://review.coreboot.org/18038
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <[email protected]>

src/mainboard/intel/leafhill/Kconfig

@@ -0,0 +1,108 @@
+
+config BOARD_GOOGLE_BASEBOARD_REEF
+	def_bool n
+	select SOC_INTEL_APOLLOLAKE
+	select BOARD_ROMSIZE_KB_16384
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_LPC
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select I2C_TPM
+	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_I2C_TPM_CR50
+	select TPM2
+	select GOOGLE_SMBIOS_MAINBOARD_VERSION
+
+if BOARD_INTEL_LEAFHILL
+
+config BASEBOARD_REEF_LAPTOP
+	def_bool n
+	select SYSTEM_TYPE_LAPTOP
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x2
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
+config DRIVER_TPM_I2C_IRQ
+	int
+	default 60 # GPE0_DW1_28
+
+config CHROMEOS
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select HAS_RECOVERY_MRC_CACHE
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+	select LID_SWITCH if BASEBOARD_REEF_LAPTOP
+
+config DRIVERS_I2C_DA7219
+	default y
+
+config DRIVERS_I2C_GENERIC
+	default y
+
+config DRIVERS_I2C_WACOM
+	default y
+
+config DRIVERS_PS2_KEYBOARD
+	default y
+
+config DRIVERS_GENERIC_GPIO_REGULATOR
+	default y
+
+config MAINBOARD_DIR
+	string
+	default intel/leafhill
+
+config VARIANT_DIR
+	string
+	default "reef"
+	default "pyro" if BOARD_GOOGLE_PYRO
+	default "snappy" if BOARD_GOOGLE_SNAPPY
+
+config DEVICETREE
+	string
+	default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO
+	default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY
+	default "variants/baseboard/devicetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Reef"
+	default "Pyro" if BOARD_GOOGLE_PYRO
+	default "Snappy" if BOARD_GOOGLE_SNAPPY
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Reef"
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "REEF TEST 3240" if BOARD_GOOGLE_REEF
+	default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO
+	default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY
+
+config MAX_CPUS
+	int
+	default 8
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config INCLUDE_NHLT_BLOBS
+	bool "Include blobs for audio."
+	select NHLT_DMIC_1CH_16B
+	select NHLT_DMIC_2CH_16B
+	select NHLT_DMIC_4CH_16B
+	select NHLT_DA7219
+	select NHLT_MAX98357
+
+config DRIVERS_GENERIC_MAX98357A
+	default y
+
+endif # BOARD_INTEL_LEAFHILL

src/mainboard/intel/leafhill/Kconfig.name

@@ -0,0 +1,4 @@
+config BOARD_INTEL_LEAFHILL
+	bool "Leafhill"
+	select BOARD_GOOGLE_BASEBOARD_REEF
+	select BASEBOARD_REEF_LAPTOP

src/mainboard/intel/leafhill/Makefile.inc

@@ -0,0 +1,19 @@
+bootblock-y += bootblock.c
+bootblock-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += boardid.c
+
+ramstage-y += boardid.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/intel/leafhill/acpi_tables.c

@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */

src/mainboard/intel/leafhill/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Reef Apollolake Reference Board
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/intel/leafhill/boardid.c

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <stddef.h>
+
+uint8_t board_id(void)
+{
+	MAYBE_STATIC int id = -1;
+
+	if (id < 0)
+		id = variant_board_id();
+
+	return id;
+}

src/mainboard/intel/leafhill/bootblock.c

@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <ec/ec.h>
+#include <soc/lpc.h>
+#include <soc/gpio.h>
+#include <variant/ec.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	lpc_configure_pads();
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+	mainboard_ec_init();
+}

src/mainboard/intel/leafhill/chromeos.c

@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+		{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH,
+			gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	/* Read PCH_WP GPIO. */
+	return gpio_get(GPIO_PCH_WP);
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}

src/mainboard/intel/leafhill/chromeos.fmd

@@ -0,0 +1,53 @@
+FLASH 16M {
+	WP_RO@0x0 0x400000 {
+		SI_DESC@0x0 0x1000
+		IFWI@0x1000 0x1ff000
+		RO_VPD@0x200000 0x4000
+		RO_SECTION@0x204000 0x1fc000 {
+			FMAP@0x0 0x800
+			RO_FRID@0x800 0x40
+			RO_FRID_PAD@0x840 0x7c0
+			COREBOOT(CBFS)@0x1000 0x17b000
+			GBB@0x17c000 0x40000
+			RO_UNUSED@0x1bc000 0x40000
+		}
+	}
+	MISC_RW@0x400000 0x30000 {
+		UNIFIED_MRC_CACHE@0x0 0x21000 {
+			RECOVERY_MRC_CACHE@0x0 0x10000
+			RW_MRC_CACHE@0x10000 0x10000
+			RW_VAR_MRC_CACHE@0x20000 0x1000
+		}
+		RW_ELOG@0x21000 0x3000
+		RW_SHARED@0x24000 0x4000 {
+			SHARED_DATA@0x0 0x2000
+			VBLOCK_DEV@0x2000 0x2000
+		}
+		RW_VPD@0x28000 0x2000
+		RW_NVRAM@0x2a000 0x6000
+	}
+	RW_SECTION_A@0x430000 0x480000 {
+		VBLOCK_A@0x0 0x10000
+		FW_MAIN_A(CBFS)@0x10000 0x46ffc0
+		RW_FWID_A@0x47ffc0 0x40
+	}
+	RW_SECTION_B@0x8b0000 0x480000 {
+		VBLOCK_B@0x0 0x10000
+		FW_MAIN_B(CBFS)@0x10000 0x46ffc0
+		RW_FWID_B@0x47ffc0 0x40
+	}
+	RW_LEGACY(CBFS)@0xd30000 0x200000
+	BIOS_UNUSABLE@0xf30000 0x4f000
+	DEVICE_EXTENSION@0xf7f000 0x80000
+	# Currently, it is required that the BIOS region be a multiple of 8KiB.
+	# This is required so that the recovery mechanism can find SIGN_CSE
+	# region aligned to 4K at the center of BIOS region. Since the
+	# descriptor at the beginning uses 4K and BIOS starts at an offset of
+	# 4K, a hole of 4K is created towards the end of the flash to compensate
+	# for the size requirement of BIOS region.
+	# FIT tool thus creates descriptor with following regions:
+	# Descriptor --> 0 to 4K
+	# BIOS       --> 4K to 0xf7f000
+	# Device ext --> 0xf7f000 to 0xfff000
+	UNUSED_HOLE@0xfff000 0x1000
+}

src/mainboard/intel/leafhill/dsdt.asl

@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	/* global NVS and variables */
+	#include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <soc/intel/apollolake/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/apollolake/acpi/northbridge.asl>
+			#include <soc/intel/apollolake/acpi/southbridge.asl>
+			#include <soc/intel/apollolake/acpi/pch_hda.asl>
+		}
+	}
+
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include <variant/acpi/dptf.asl>
+		/* Include soc specific DPTF changes */
+		#include <soc/intel/apollolake/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <soc/intel/common/acpi/dptf/dptf.asl>
+	}
+}