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RISC-V CPU Core (RV32IM)

Verilog 1,309 239 Updated Sep 18, 2021

Linux Kernel Programming 2E - published by Packt

Makefile 321 80 Updated Jan 3, 2025

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

SystemVerilog 57 6 Updated Nov 28, 2024

A self-paced course to learn Rust, one exercise at a time.

Rust 6,486 1,188 Updated Dec 18, 2024

RISC-V IOMMU Specification

C 101 18 Updated Dec 25, 2024

A small, light weight, RISC CPU soft core

Verilog 1,333 157 Updated Nov 30, 2024

Waveform Viewer Extension for VScode

TypeScript 86 3 Updated Jan 3, 2025

Instruction Set Generator initially contributed by Futurewei

C++ 268 61 Updated Oct 17, 2023