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Merge branches 'pm-core', 'powercap', 'pm-opp', 'pm-avs' and 'pm-misc'
* pm-core: PM-runtime: add tracepoints for usage_count changes * powercap: powercap/intel_rapl: add support for JasperLake x86/cpu: Add Jasper Lake to Intel family powercap/intel_rapl: add support for TigerLake Mobile * pm-opp: opp: Replace list_kref with a local counter opp: Free static OPPs on errors while adding them * pm-avs: power: avs: qcom-cpr: remove duplicated include from qcom-cpr.c power: avs: fix uninitialized error return on failed cpr_read_fuse_uV() call power: avs: qcom-cpr: make cpr_get_opp_hz_for_req() static power: avs: qcom-cpr: remove set but unused variable power: avs: qcom-cpr: make sure that regmap is available power: avs: qcom-cpr: fix unsigned expression compared with zero power: avs: qcom-cpr: fix invalid printk specifier in debug print power: avs: Add support for CPR (Core Power Reduction) dt-bindings: power: avs: Add support for CPR (Core Power Reduction) * pm-misc: mailmap: Add entry for <[email protected]>
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@@ -217,6 +217,7 @@ Praveen BP <[email protected]> | |
Punit Agrawal <[email protected]> <[email protected]> | ||
Qais Yousef <[email protected]> <[email protected]> | ||
Quentin Perret <[email protected]> <[email protected]> | ||
Rafael J. Wysocki <[email protected]> <[email protected]> | ||
Rajesh Shah <[email protected]> | ||
Ralf Baechle <[email protected]> | ||
Ralf Wildenhues <[email protected]> | ||
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Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
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QCOM CPR (Core Power Reduction) | ||
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||
CPR (Core Power Reduction) is a technology to reduce core power on a CPU | ||
or other device. Each OPP of a device corresponds to a "corner" that has | ||
a range of valid voltages for a particular frequency. While the device is | ||
running at a particular frequency, CPR monitors dynamic factors such as | ||
temperature, etc. and suggests adjustments to the voltage to save power | ||
and meet silicon characteristic requirements. | ||
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||
- compatible: | ||
Usage: required | ||
Value type: <string> | ||
Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 | ||
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||
- reg: | ||
Usage: required | ||
Value type: <prop-encoded-array> | ||
Definition: base address and size of the rbcpr register region | ||
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||
- interrupts: | ||
Usage: required | ||
Value type: <prop-encoded-array> | ||
Definition: should specify the CPR interrupt | ||
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- clocks: | ||
Usage: required | ||
Value type: <prop-encoded-array> | ||
Definition: phandle to the reference clock | ||
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- clock-names: | ||
Usage: required | ||
Value type: <stringlist> | ||
Definition: must be "ref" | ||
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- vdd-apc-supply: | ||
Usage: required | ||
Value type: <phandle> | ||
Definition: phandle to the vdd-apc-supply regulator | ||
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- #power-domain-cells: | ||
Usage: required | ||
Value type: <u32> | ||
Definition: should be 0 | ||
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- operating-points-v2: | ||
Usage: required | ||
Value type: <phandle> | ||
Definition: A phandle to the OPP table containing the | ||
performance states supported by the CPR | ||
power domain | ||
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- acc-syscon: | ||
Usage: optional | ||
Value type: <phandle> | ||
Definition: phandle to syscon for writing ACC settings | ||
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- nvmem-cells: | ||
Usage: required | ||
Value type: <phandle> | ||
Definition: phandle to nvmem cells containing the data | ||
that makes up a fuse corner, for each fuse corner. | ||
As well as the CPR fuse revision. | ||
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- nvmem-cell-names: | ||
Usage: required | ||
Value type: <stringlist> | ||
Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", | ||
"cpr_quotient_offset3", "cpr_init_voltage1", | ||
"cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", | ||
"cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", | ||
"cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" | ||
for qcs404. | ||
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Example: | ||
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cpr_opp_table: cpr-opp-table { | ||
compatible = "operating-points-v2-qcom-level"; | ||
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cpr_opp1: opp1 { | ||
opp-level = <1>; | ||
qcom,opp-fuse-level = <1>; | ||
}; | ||
cpr_opp2: opp2 { | ||
opp-level = <2>; | ||
qcom,opp-fuse-level = <2>; | ||
}; | ||
cpr_opp3: opp3 { | ||
opp-level = <3>; | ||
qcom,opp-fuse-level = <3>; | ||
}; | ||
}; | ||
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power-controller@b018000 { | ||
compatible = "qcom,qcs404-cpr", "qcom,cpr"; | ||
reg = <0x0b018000 0x1000>; | ||
interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; | ||
clocks = <&xo_board>; | ||
clock-names = "ref"; | ||
vdd-apc-supply = <&pms405_s3>; | ||
#power-domain-cells = <0>; | ||
operating-points-v2 = <&cpr_opp_table>; | ||
acc-syscon = <&tcsr>; | ||
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nvmem-cells = <&cpr_efuse_quot_offset1>, | ||
<&cpr_efuse_quot_offset2>, | ||
<&cpr_efuse_quot_offset3>, | ||
<&cpr_efuse_init_voltage1>, | ||
<&cpr_efuse_init_voltage2>, | ||
<&cpr_efuse_init_voltage3>, | ||
<&cpr_efuse_quot1>, | ||
<&cpr_efuse_quot2>, | ||
<&cpr_efuse_quot3>, | ||
<&cpr_efuse_ring1>, | ||
<&cpr_efuse_ring2>, | ||
<&cpr_efuse_ring3>, | ||
<&cpr_efuse_revision>; | ||
nvmem-cell-names = "cpr_quotient_offset1", | ||
"cpr_quotient_offset2", | ||
"cpr_quotient_offset3", | ||
"cpr_init_voltage1", | ||
"cpr_init_voltage2", | ||
"cpr_init_voltage3", | ||
"cpr_quotient1", | ||
"cpr_quotient2", | ||
"cpr_quotient3", | ||
"cpr_ring_osc1", | ||
"cpr_ring_osc2", | ||
"cpr_ring_osc3", | ||
"cpr_fuse_revision"; | ||
}; |
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@@ -13671,6 +13671,14 @@ S: Maintained | |
F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | ||
F: drivers/cpufreq/qcom-cpufreq-nvmem.c | ||
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||
QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER | ||
M: Niklas Cassel <[email protected]> | ||
L: [email protected] | ||
L: [email protected] | ||
S: Maintained | ||
F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt | ||
F: drivers/power/avs/qcom-cpr.c | ||
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QUALCOMM EMAC GIGABIT ETHERNET DRIVER | ||
M: Timur Tabi <[email protected]> | ||
L: [email protected] | ||
|
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