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arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bi…
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…ndings at the same time
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@aquynh
aquynh committed Jun 17, 2014
1 parent 8693fcd commit 73bbbb3
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Showing 5 changed files with 589 additions and 291 deletions.
286 changes: 286 additions & 0 deletions arch/ARM/ARMMapping.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3196,6 +3196,54 @@ static insn_map insns[] = {
ARM_VCEQv8i8, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv16i8, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv2f32, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv2i32, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv4f32, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv4i16, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv4i32, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv8i16, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCEQzv8i8, ARM_INS_VCEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -3280,6 +3328,54 @@ static insn_map insns[] = {
ARM_VCGEuv8i8, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv16i8, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv2f32, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv2i32, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv4f32, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv4i16, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv4i32, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv8i16, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGEzv8i8, ARM_INS_VCGE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -3364,6 +3460,102 @@ static insn_map insns[] = {
ARM_VCGTuv8i8, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv16i8, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv2f32, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv2i32, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv4f32, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv4i16, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv4i32, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv8i16, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCGTzv8i8, ARM_INS_VCGT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv16i8, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv2f32, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv2i32, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv4f32, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv4i16, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv4i32, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv8i16, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLEzv8i8, ARM_INS_VCLE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -3400,6 +3592,54 @@ static insn_map insns[] = {
ARM_VCLSv8i8, ARM_INS_VCLS,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv16i8, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv2f32, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv2i32, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv4f32, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv4i16, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv4i32, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv8i16, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
ARM_VCLTzv8i8, ARM_INS_VCLT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -3454,12 +3694,36 @@ static insn_map insns[] = {
ARM_VCMPES, ARM_INS_VCMPE,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
#endif
},
{
ARM_VCMPEZD, ARM_INS_VCMPE,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
#endif
},
{
ARM_VCMPEZS, ARM_INS_VCMPE,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
#endif
},
{
ARM_VCMPS, ARM_INS_VCMP,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
#endif
},
{
ARM_VCMPZD, ARM_INS_VCMP,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
#endif
},
{
ARM_VCMPZS, ARM_INS_VCMP,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -11326,6 +11590,18 @@ static insn_map insns[] = {
ARM_t2MOVr, ARM_INS_MOV,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2MOVsra_flag, ARM_INS_ASRS,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2MOVsrl_flag, ARM_INS_LSRS,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -13000,6 +13276,12 @@ static insn_map insns[] = {
ARM_tROR, ARM_INS_ROR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
#endif
},
{
ARM_tRSB, ARM_INS_RSB,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
#endif
},
{
Expand Down Expand Up @@ -13443,7 +13725,9 @@ static name_map insn_name_maps[] = {
{ ARM_INS_VCEQ, "vceq" },
{ ARM_INS_VCGE, "vcge" },
{ ARM_INS_VCGT, "vcgt" },
{ ARM_INS_VCLE, "vcle" },
{ ARM_INS_VCLS, "vcls" },
{ ARM_INS_VCLT, "vclt" },
{ ARM_INS_VCLZ, "vclz" },
{ ARM_INS_VCMP, "vcmp" },
{ ARM_INS_VCMPE, "vcmpe" },
Expand Down Expand Up @@ -13575,6 +13859,8 @@ static name_map insn_name_maps[] = {
{ ARM_INS_IT, "it" },
{ ARM_INS_LSL, "lsl" },
{ ARM_INS_LSR, "lsr" },
{ ARM_INS_ASRS, "asrs" },
{ ARM_INS_LSRS, "lsrs" },
{ ARM_INS_ORN, "orn" },
{ ARM_INS_ROR, "ror" },
{ ARM_INS_RRX, "rrx" },
Expand Down
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