change cs_disasm() and cs_disasm_dyn() to be portable API. fix relate…

…d code using these API
pfalcon · Nov 29, 2013 · b42a657 · b42a657
1 parent 0b6f1bd
commit b42a657
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Showing 20 changed files with 151 additions and 151 deletions.
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
@@ -226,9 +226,9 @@ void AArch64_init(MCRegisterInfo *MRI)
 
 
 static DecodeStatus _getInstruction(MCInst *MI,
-		unsigned char *code, uint64_t code_len,
+		unsigned char *code, size_t code_len,
 		uint16_t *Size,
-		uint64_t Address, MCRegisterInfo *MRI)
+		size_t Address, MCRegisterInfo *MRI)
 {
 	if (code_len < 4) {
 		// not enough data
@@ -254,10 +254,10 @@ static DecodeStatus _getInstruction(MCInst *MI,
 	return MCDisassembler_Fail;
 }
 
-bool AArch64_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info)
+bool AArch64_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr, uint16_t *size, size_t address, void *info)
 {
 	DecodeStatus status = _getInstruction(instr,
-			(unsigned char *)code, code_len,
+			code, code_len,
 			size,
 			address, (MCRegisterInfo *)info);
 

diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
@@ -12,8 +12,8 @@
 
 void AArch64_init(MCRegisterInfo *MRI);
 
-bool AArch64_getInstruction(csh ud, char *code, uint64_t code_len,
-		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+bool AArch64_getInstruction(csh ud, unsigned char *code, size_t code_len,
+		MCInst *instr, uint16_t *size, size_t address, void *info);
 
 #endif
 
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
@@ -422,8 +422,8 @@ void ARM_init(MCRegisterInfo *MRI)
 			0);
 }
 
-static DecodeStatus _ARM_getInstruction(MCInst *MI, char *code, uint64_t code_len,
-		uint16_t *Size, uint64_t Address)
+static DecodeStatus _ARM_getInstruction(MCInst *MI, unsigned char *code, size_t code_len,
+		uint16_t *Size, size_t Address)
 {
 	uint8_t bytes[4];
 
@@ -644,8 +644,8 @@ static void UpdateThumbVFPPredicate(MCInst *MI)
 	}
 }
 
-static DecodeStatus _Thumb_getInstruction(MCInst *MI, char *code, uint64_t code_len,
-		uint16_t *Size, uint64_t Address)
+static DecodeStatus _Thumb_getInstruction(MCInst *MI, unsigned char *code, size_t code_len,
+		uint16_t *Size, size_t Address)
 {
 	uint8_t bytes[4];
 
@@ -821,17 +821,17 @@ static DecodeStatus _Thumb_getInstruction(MCInst *MI, char *code, uint64_t code_
 	return MCDisassembler_Fail;
 }
 
-bool Thumb_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
+bool Thumb_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr,
+		uint16_t *size, size_t address, void *info)
 {
 	//cs_struct *handle = (cs_struct *)ud;
 	DecodeStatus status = _Thumb_getInstruction(instr, code, code_len, size, address);
 
 	return status == MCDisassembler_Success;
 }
 
-bool ARM_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
+bool ARM_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr,
+		uint16_t *size, size_t address, void *info)
 {
 	//cs_struct *handle = (cs_struct *)ud;
 	DecodeStatus status = _ARM_getInstruction(instr, code, code_len, size, address);

diff --git a/arch/ARM/ARMDisassembler.h b/arch/ARM/ARMDisassembler.h
@@ -9,8 +9,8 @@
 
 void ARM_init(MCRegisterInfo *MRI);
 
-bool ARM_getInstruction(csh handle, char *code, uint64_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+bool ARM_getInstruction(csh handle, unsigned char *code, size_t code_len, MCInst *instr, uint16_t *size, size_t address, void *info);
 
-bool Thumb_getInstruction(csh handle, char *code, uint64_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+bool Thumb_getInstruction(csh handle, unsigned char *code, size_t code_len, MCInst *instr, uint16_t *size, size_t address, void *info);
 
 #endif
diff --git a/arch/ARM/ARMGenDisassemblerTables.inc b/arch/ARM/ARMGenDisassemblerTables.inc
@@ -13448,7 +13448,7 @@ DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
 
 #define DecodeInstruction(fname, fieldname, decoder, InsnType) \
 static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
-                                      InsnType insn, uint64_t Address, \
+                                      InsnType insn, size_t Address, \
                                       int feature) \
 { \
   uint64_t Bits = ARM_getFeatureBits(feature); \

diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
@@ -163,7 +163,7 @@ static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc,
 
 	//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
 	SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc));
-	MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count - 1].shift.type = ShOpc;
+	MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
 
 	if (ShOpc != ARM_AM_rrx) {
 		SStream_concat(O, " ");
@@ -342,7 +342,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
 		SStream_concat(O, ", %s", markup("<imm:"));
 		SStream_concat(O, "#0x%x", translateShiftImm(getSORegOffset(MCOperand_getImm(MO2))));
 		SStream_concat(O, markup(">"));
-		MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count - 1].shift.type = ARM_AM_getSORegShOp(MCOperand_getImm(MO2));
+		MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count - 1].shift.type = (arm_shifter)ARM_AM_getSORegShOp(MCOperand_getImm(MO2));
 		MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count - 1].shift.value = translateShiftImm(getSORegOffset(MCOperand_getImm(MO2)));
 		return;
 	}
@@ -622,7 +622,7 @@ static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
 		if (getAM2Offset(MCOperand_getImm(MO3))) { // Don't print +0.
 			SStream_concat(O, ", %s", markup("<imm:"));
 			SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), getAM2Offset(MCOperand_getImm(MO3)));
-			MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count].shift.type = getAM2Op(MCOperand_getImm(MO3));
+			MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op(MCOperand_getImm(MO3));
 			MI->pub_insn.arm.operands[MI->pub_insn.arm.op_count].shift.value = getAM2Offset(MCOperand_getImm(MO3));
 			SStream_concat(O, markup(">"));
 		}

diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
@@ -243,9 +243,9 @@ static DecodeStatus readInstruction32(unsigned char *code, uint32_t *insn, bool
 }
 
 static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
-		char *code, uint64_t code_len,
+		unsigned char *code, size_t code_len,
 		uint16_t *Size,
-		uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI,
+		size_t Address, bool isBigEndian, MCRegisterInfo *MRI,
 		bool isMicroMips)
 {
 	uint32_t Insn;
@@ -279,8 +279,8 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 	return MCDisassembler_Fail;
 }
 
-bool Mips_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
+bool Mips_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr,
+		uint16_t *size, size_t address, void *info)
 {
 	cs_struct *handle = (cs_struct *)(uintptr_t)ud;
 
@@ -294,9 +294,9 @@ bool Mips_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr,
 }
 
 static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr,
-		char *code, uint64_t code_len,
+		unsigned char *code, size_t code_len,
 		uint16_t *Size,
-		uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
+		size_t Address, bool isBigEndian, MCRegisterInfo *MRI)
 {
 	uint32_t Insn;
 
@@ -320,8 +320,8 @@ static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr,
 	return MCDisassembler_Fail;
 }
 
-bool Mips64_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
+bool Mips64_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr,
+		uint16_t *size, size_t address, void *info)
 {
 	cs_struct *handle = (cs_struct *)(uintptr_t)ud;
 

diff --git a/arch/Mips/MipsDisassembler.h b/arch/Mips/MipsDisassembler.h
@@ -11,10 +11,10 @@
 
 void Mips_init(MCRegisterInfo *MRI);
 
-bool Mips_getInstruction(csh handle, char *code, uint64_t code_len,
-		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+bool Mips_getInstruction(csh handle, unsigned char *code, size_t code_len,
+		MCInst *instr, uint16_t *size, size_t address, void *info);
 
-bool Mips64_getInstruction(csh handle, char *code, uint64_t code_len,
-		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+bool Mips64_getInstruction(csh handle, unsigned char *code, size_t code_len,
+		MCInst *instr, uint16_t *size, size_t address, void *info);
 
 #endif
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
@@ -35,7 +35,7 @@
 #include "X86GenInstrInfo.inc"
 
 struct reader_info {
-	char *code;
+	unsigned char *code;
 	uint64_t size;
 	uint64_t offset;
 };
@@ -611,7 +611,7 @@ static void update_pub_insn(cs_insn *pub, InternalInstruction *inter)
 }
 
 // Public interface for the disassembler
-bool X86_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *_info)
+bool X86_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr, uint16_t *size, size_t address, void *_info)
 {
 	cs_struct *handle = (cs_struct *)(uintptr_t)ud;
 	InternalInstruction insn;

diff --git a/arch/X86/X86Disassembler.h b/arch/X86/X86Disassembler.h
@@ -95,7 +95,7 @@
 #undef INSTRUCTION_SPECIFIER_FIELDS
 #undef INSTRUCTION_IDS
 
-bool X86_getInstruction(csh handle, char *code, uint64_t code_len,
-		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+bool X86_getInstruction(csh handle, unsigned char *code, size_t code_len,
+		MCInst *instr, uint16_t *size, size_t address, void *info);
 
 #endif
diff --git a/cs.c b/cs.c
@@ -189,12 +189,12 @@ static void fill_insn(cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mc
 	insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0';
 }
 
-uint64_t cs_disasm(csh ud, char *buffer, uint64_t size, uint64_t offset, uint64_t count, cs_insn *insn)
+size_t cs_disasm(csh ud, unsigned char *buffer, size_t size, size_t offset, size_t count, cs_insn *insn)
 {
 	cs_struct *handle = (cs_struct *)(uintptr_t)ud;
 	MCInst mci;
 	uint16_t insn_size;
-	uint64_t c = 0;
+	size_t c = 0;
 
 	if (!handle) {
 		// FIXME: handle this case?
@@ -238,15 +238,15 @@ uint64_t cs_disasm(csh ud, char *buffer, uint64_t size, uint64_t offset, uint64_
 
 // dynamicly allocate memory to contain disasm insn
 // NOTE: caller must free() the allocated memory itself to avoid memory leaking
-uint64_t cs_disasm_dyn(csh ud, char *buffer, uint64_t size, uint64_t offset, uint64_t count, cs_insn **insn)
+size_t cs_disasm_dyn(csh ud, unsigned char *buffer, size_t size, size_t offset, size_t count, cs_insn **insn)
 {
 	cs_struct *handle = (cs_struct *)(uintptr_t)ud;
 	MCInst mci;
 	uint16_t insn_size;
-	uint64_t c = 0, f = 0;
+	size_t c = 0, f = 0;
 	cs_insn insn_cache[64];
 	void *total = NULL;
-	uint64_t total_size = 0;
+	size_t total_size = 0;
 
 	if (!handle) {
 		// FIXME: how to handle this case:

diff --git a/cs_priv.h b/cs_priv.h
@@ -15,7 +15,7 @@ typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
 // this is the best time to gather insn's characteristics
 typedef void (*PostPrinter_t)(unsigned int insn, cs_insn *, char *mnem);
 
-typedef bool (*Disasm_t)(csh handle, char *code, uint64_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+typedef bool (*Disasm_t)(csh handle, unsigned char *code, size_t code_len, MCInst *instr, uint16_t *size, size_t address, void *info);
 
 typedef char *(*GetName_t)(unsigned int reg);
 

diff --git a/include/arm.h b/include/arm.h
@@ -62,7 +62,7 @@ typedef struct arm_op_mem {
 	unsigned int base;	// base register
 	unsigned int index;	// index register
 	int scale;	// scale for index register (can be 1, or -1)
-	int64_t disp;	// displacement/offset value
+	int disp;	// displacement/offset value
 } arm_op_mem;
 
 // Instruction operand
@@ -74,7 +74,7 @@ typedef struct cs_arm_op {
 	arm_op_type type;	// operand type
 	union {
 		unsigned int reg;	// register value for REG operand
-		int64_t imm;		// immediate value for C-IMM, P-IMM or IMM operand
+		unsigned int imm;		// immediate value for C-IMM, P-IMM or IMM operand
 		double fp;			// floating point value for FP operand
 		arm_op_mem mem;		// base/index/scale/disp value for MEM operand
 	};

diff --git a/include/capstone.h b/include/capstone.h
@@ -12,7 +12,7 @@ extern "C" {
 #include <stdbool.h>
 
 // Handle using with all API
-typedef uint64_t csh;
+typedef size_t csh;
 
 // Architecture type
 typedef enum cs_arch {
@@ -52,7 +52,7 @@ typedef struct cs_insn {
 	unsigned int id;
 
 	// Offset address of this instruction
-	uint64_t address;
+	size_t address;
 
 	// Size of this instruction
 	uint16_t size;	
@@ -144,10 +144,10 @@ cs_err cs_errno(csh handle);
  @return: the number of succesfully disassembled instructions,
  or 0 if this function failed to disassemble the given code
 */
-uint64_t cs_disasm(csh handle,
-		char *code, uint64_t code_size,
-		uint64_t offset,
-		uint64_t count,
+size_t cs_disasm(csh handle,
+		unsigned char *code, size_t code_size,
+		size_t offset,
+		size_t count,
 		cs_insn *insn);
 
 /*
@@ -168,10 +168,10 @@ uint64_t cs_disasm(csh handle,
  @return: the number of succesfully disassembled instructions,
  or 0 if this function failed to disassemble the given code
 */
-uint64_t cs_disasm_dyn(csh handle,
-		char *code, uint64_t code_size,
-		uint64_t offset,
-		uint64_t count,
+size_t cs_disasm_dyn(csh handle,
+		unsigned char *code, size_t code_size,
+		size_t offset,
+		size_t count,
 		cs_insn **insn);
 
 /*