drivers: serial: uart_altera: add driver

Add driver for altera avalon uart core.

Signed-off-by: Goh Shun Jing <[email protected]>

drivers/serial/CMakeLists.txt

@@ -2,6 +2,7 @@
 
 zephyr_library()
 zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag.c)
+zephyr_library_sources_ifdef(CONFIG_UART_ALTERA uart_altera.c)
 zephyr_library_sources_ifdef(CONFIG_UART_TELINK_B91 uart_b91.c)
 zephyr_library_sources_ifdef(CONFIG_UART_IMX uart_imx.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ITE_IT8XXX2 uart_ite_it8xxx2.c)

drivers/serial/Kconfig

@@ -210,4 +210,6 @@ source "drivers/serial/Kconfig.cdns"
 
 source "drivers/serial/Kconfig.opentitan"
 
+source "drivers/serial/Kconfig.altera"
+
 endif # SERIAL

drivers/serial/Kconfig.altera

@@ -0,0 +1,24 @@
+# Copyright (c) 2023 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_ALTERA
+	bool "ALTERA UART driver"
+	depends on DT_HAS_ALTR_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	help
+	  Enable the Altera UART driver, that can be built into Intel NiosV CPU designs.
+
+config UART_ALTERA_EOP
+	bool "ALTERA UART end of packet feature"
+	depends on UART_ALTERA && UART_DRV_CMD && UART_INTERRUPT_DRIVEN
+	help
+	  Use driver command CMD_ENABLE_EOP and CMD_DISABLE_EOP to use the feature.
+
+config UART_ALTERA_LINE_CTRL_WORKAROUND
+	bool "ALTERA UART flow control workaround"
+	depends on UART_ALTERA && UART_LINE_CTRL
+	help
+	  Before enabling this, please try to optimise the ISR to fetch the receive data faster.
+	  Enabling this will cause the transmitter to wait for rising edge of CTS before sending.
+	  The receiver will deassert RTS as soon as a byte is received and reassert after the byte is fetched.