opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RoCE v2 hardware and software implementation

NetworkDirect Service Provider Interface

TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

The hardware implementation of UDP in Bluespec SystemVerilog

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

RDMA programming example

Public repository for PicoEVB (Xilinx Artix XC7A50T based)

Verilog AXI stream components for FPGA implementation

Verilog Ethernet components for FPGA implementation

XDP speeds up networking on Windows

A bounded single-producer single-consumer wait-free and lock-free queue written in C++11

A collection of resources on wait-free and lock-free programming

A bounded multi-producer multi-consumer concurrent queue written in C++11

Verilog Ethernet Switch (layer 2)