Hardcaml is an OCaml library for designing hardware.

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

A computer for human beings.

Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL

Universal utility for programming FPGA

A modern hardware definition language and toolchain based on Python

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

UNIX-like reverse engineering framework and command-line toolset

4 stage, in-order, compute RISC-V core based on the CV32E40P

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

PicoRV32 - A Size-Optimized RISC-V CPU

tiniest x86-64-linux emulator

🌊 Digital timing diagram rendering engine

Animation engine for explanatory math videos