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Be more aggressive with X-values in the testbench
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Signed-off-by: Claire Xenia Wolf <[email protected]>
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clairexen committed Oct 21, 2020
1 parent f2a8b32 commit 8bb5a6c
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Showing 2 changed files with 6 additions and 5 deletions.
7 changes: 4 additions & 3 deletions nerv.sv
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,8 @@
*/

module nerv #(
parameter [31:0] RESET_ADDR = 32'h 0000_0000
parameter [31:0] RESET_ADDR = 32'h 0000_0000,
parameter integer NUMREGS = 32
) (
input clock,
input reset,
Expand Down Expand Up @@ -85,10 +86,10 @@ module nerv #(

assign dmem_valid = mem_wr_enable || mem_rd_enable;
assign dmem_addr = mem_wr_enable ? mem_wr_addr : mem_rd_enable ? mem_rd_addr : 32'h x;
assign dmem_wstrb = mem_wr_enable ? mem_wr_strb : 4'h 0;
assign dmem_wstrb = mem_wr_enable ? mem_wr_strb : mem_rd_enable ? 4'h 0 : 4'h x;
assign dmem_wdata = mem_wr_enable ? mem_wr_data : 32'h x;

reg [31:0] regfile [0:31];
reg [31:0] regfile [0:NUMREGS-1];
wire [31:0] insn;
reg [31:0] npc;
reg [31:0] pc;
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4 changes: 2 additions & 2 deletions testbench.sv
Original file line number Diff line number Diff line change
Expand Up @@ -120,13 +120,13 @@ nerv dut (
.stall(stall),

.imem_addr(imem_addr),
.imem_data(imem_data),
.imem_data(stall ? 32'bx : imem_data),

.dmem_valid(dmem_valid),
.dmem_addr(dmem_addr),
.dmem_wstrb(dmem_wstrb),
.dmem_wdata(dmem_wdata),
.dmem_rdata(dmem_rdata)
.dmem_rdata(stall ? 32'bx : dmem_rdata)
);

reg [31:0] cycles = 0;
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