Skip to content

Commit

Permalink
powerpc/32s: fix suspend/resume when IBATs 4-7 are used
Browse files Browse the repository at this point in the history 
commit 6ecb78e upstream.

Previously, only IBAT1 and IBAT2 were used to map kernel linear mem.
Since commit 63b2bc6 ("powerpc/mm/32s: Use BATs for
STRICT_KERNEL_RWX"), we may have all 8 BATs used for mapping
kernel text. But the suspend/restore functions only save/restore
BATs 0 to 3, and clears BATs 4 to 7.

Make suspend and restore functions respectively save and reload
the 8 BATs on CPUs having MMU_FTR_USE_HIGH_BATS feature.

Reported-by: Andreas Schwab <[email protected]>
Cc: [email protected]
Signed-off-by: Christophe Leroy <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
  • Loading branch information
@chleroy @gregkh
chleroy authored and gregkh committed Jul 31, 2019
1 parent a6766bb commit ce32ed9
Show file tree
Hide file tree
Showing 2 changed files with 128 additions and 13 deletions.
73 changes: 65 additions & 8 deletions arch/powerpc/kernel/swsusp_32.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,11 +24,19 @@
#define SL_IBAT2 0x48
#define SL_DBAT3 0x50
#define SL_IBAT3 0x58
#define SL_TB 0x60
#define SL_R2 0x68
#define SL_CR 0x6c
#define SL_LR 0x70
#define SL_R12 0x74 /* r12 to r31 */
#define SL_DBAT4 0x60
#define SL_IBAT4 0x68
#define SL_DBAT5 0x70
#define SL_IBAT5 0x78
#define SL_DBAT6 0x80
#define SL_IBAT6 0x88
#define SL_DBAT7 0x90
#define SL_IBAT7 0x98
#define SL_TB 0xa0
#define SL_R2 0xa8
#define SL_CR 0xac
#define SL_LR 0xb0
#define SL_R12 0xb4 /* r12 to r31 */
#define SL_SIZE (SL_R12 + 80)

.section .data
Expand Down Expand Up @@ -113,6 +121,41 @@ _GLOBAL(swsusp_arch_suspend)
mfibatl r4,3
stw r4,SL_IBAT3+4(r11)

BEGIN_MMU_FTR_SECTION
mfspr r4,SPRN_DBAT4U
stw r4,SL_DBAT4(r11)
mfspr r4,SPRN_DBAT4L
stw r4,SL_DBAT4+4(r11)
mfspr r4,SPRN_DBAT5U
stw r4,SL_DBAT5(r11)
mfspr r4,SPRN_DBAT5L
stw r4,SL_DBAT5+4(r11)
mfspr r4,SPRN_DBAT6U
stw r4,SL_DBAT6(r11)
mfspr r4,SPRN_DBAT6L
stw r4,SL_DBAT6+4(r11)
mfspr r4,SPRN_DBAT7U
stw r4,SL_DBAT7(r11)
mfspr r4,SPRN_DBAT7L
stw r4,SL_DBAT7+4(r11)
mfspr r4,SPRN_IBAT4U
stw r4,SL_IBAT4(r11)
mfspr r4,SPRN_IBAT4L
stw r4,SL_IBAT4+4(r11)
mfspr r4,SPRN_IBAT5U
stw r4,SL_IBAT5(r11)
mfspr r4,SPRN_IBAT5L
stw r4,SL_IBAT5+4(r11)
mfspr r4,SPRN_IBAT6U
stw r4,SL_IBAT6(r11)
mfspr r4,SPRN_IBAT6L
stw r4,SL_IBAT6+4(r11)
mfspr r4,SPRN_IBAT7U
stw r4,SL_IBAT7(r11)
mfspr r4,SPRN_IBAT7L
stw r4,SL_IBAT7+4(r11)
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)

#if 0
/* Backup various CPU config stuffs */
bl __save_cpu_setup
Expand Down Expand Up @@ -278,27 +321,41 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
mtibatu 3,r4
lwz r4,SL_IBAT3+4(r11)
mtibatl 3,r4
#endif

BEGIN_MMU_FTR_SECTION
li r4,0
lwz r4,SL_DBAT4(r11)
mtspr SPRN_DBAT4U,r4
lwz r4,SL_DBAT4+4(r11)
mtspr SPRN_DBAT4L,r4
lwz r4,SL_DBAT5(r11)
mtspr SPRN_DBAT5U,r4
lwz r4,SL_DBAT5+4(r11)
mtspr SPRN_DBAT5L,r4
lwz r4,SL_DBAT6(r11)
mtspr SPRN_DBAT6U,r4
lwz r4,SL_DBAT6+4(r11)
mtspr SPRN_DBAT6L,r4
lwz r4,SL_DBAT7(r11)
mtspr SPRN_DBAT7U,r4
lwz r4,SL_DBAT7+4(r11)
mtspr SPRN_DBAT7L,r4
lwz r4,SL_IBAT4(r11)
mtspr SPRN_IBAT4U,r4
lwz r4,SL_IBAT4+4(r11)
mtspr SPRN_IBAT4L,r4
lwz r4,SL_IBAT5(r11)
mtspr SPRN_IBAT5U,r4
lwz r4,SL_IBAT5+4(r11)
mtspr SPRN_IBAT5L,r4
lwz r4,SL_IBAT6(r11)
mtspr SPRN_IBAT6U,r4
lwz r4,SL_IBAT6+4(r11)
mtspr SPRN_IBAT6L,r4
lwz r4,SL_IBAT7(r11)
mtspr SPRN_IBAT7U,r4
lwz r4,SL_IBAT7+4(r11)
mtspr SPRN_IBAT7L,r4
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
#endif

/* Flush all TLBs */
lis r4,0x1000
Expand Down
68 changes: 63 additions & 5 deletions arch/powerpc/platforms/powermac/sleep.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,18 @@
#define SL_IBAT2 0x48
#define SL_DBAT3 0x50
#define SL_IBAT3 0x58
#define SL_TB 0x60
#define SL_R2 0x68
#define SL_CR 0x6c
#define SL_R12 0x70 /* r12 to r31 */
#define SL_DBAT4 0x60
#define SL_IBAT4 0x68
#define SL_DBAT5 0x70
#define SL_IBAT5 0x78
#define SL_DBAT6 0x80
#define SL_IBAT6 0x88
#define SL_DBAT7 0x90
#define SL_IBAT7 0x98
#define SL_TB 0xa0
#define SL_R2 0xa8
#define SL_CR 0xac
#define SL_R12 0xb0 /* r12 to r31 */
#define SL_SIZE (SL_R12 + 80)

.section .text
Expand Down Expand Up @@ -125,6 +133,41 @@ _GLOBAL(low_sleep_handler)
mfibatl r4,3
stw r4,SL_IBAT3+4(r1)

BEGIN_MMU_FTR_SECTION
mfspr r4,SPRN_DBAT4U
stw r4,SL_DBAT4(r1)
mfspr r4,SPRN_DBAT4L
stw r4,SL_DBAT4+4(r1)
mfspr r4,SPRN_DBAT5U
stw r4,SL_DBAT5(r1)
mfspr r4,SPRN_DBAT5L
stw r4,SL_DBAT5+4(r1)
mfspr r4,SPRN_DBAT6U
stw r4,SL_DBAT6(r1)
mfspr r4,SPRN_DBAT6L
stw r4,SL_DBAT6+4(r1)
mfspr r4,SPRN_DBAT7U
stw r4,SL_DBAT7(r1)
mfspr r4,SPRN_DBAT7L
stw r4,SL_DBAT7+4(r1)
mfspr r4,SPRN_IBAT4U
stw r4,SL_IBAT4(r1)
mfspr r4,SPRN_IBAT4L
stw r4,SL_IBAT4+4(r1)
mfspr r4,SPRN_IBAT5U
stw r4,SL_IBAT5(r1)
mfspr r4,SPRN_IBAT5L
stw r4,SL_IBAT5+4(r1)
mfspr r4,SPRN_IBAT6U
stw r4,SL_IBAT6(r1)
mfspr r4,SPRN_IBAT6L
stw r4,SL_IBAT6+4(r1)
mfspr r4,SPRN_IBAT7U
stw r4,SL_IBAT7(r1)
mfspr r4,SPRN_IBAT7L
stw r4,SL_IBAT7+4(r1)
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)

/* Backup various CPU config stuffs */
bl __save_cpu_setup

Expand Down Expand Up @@ -325,22 +368,37 @@ grackle_wake_up:
mtibatl 3,r4

BEGIN_MMU_FTR_SECTION
li r4,0
lwz r4,SL_DBAT4(r1)
mtspr SPRN_DBAT4U,r4
lwz r4,SL_DBAT4+4(r1)
mtspr SPRN_DBAT4L,r4
lwz r4,SL_DBAT5(r1)
mtspr SPRN_DBAT5U,r4
lwz r4,SL_DBAT5+4(r1)
mtspr SPRN_DBAT5L,r4
lwz r4,SL_DBAT6(r1)
mtspr SPRN_DBAT6U,r4
lwz r4,SL_DBAT6+4(r1)
mtspr SPRN_DBAT6L,r4
lwz r4,SL_DBAT7(r1)
mtspr SPRN_DBAT7U,r4
lwz r4,SL_DBAT7+4(r1)
mtspr SPRN_DBAT7L,r4
lwz r4,SL_IBAT4(r1)
mtspr SPRN_IBAT4U,r4
lwz r4,SL_IBAT4+4(r1)
mtspr SPRN_IBAT4L,r4
lwz r4,SL_IBAT5(r1)
mtspr SPRN_IBAT5U,r4
lwz r4,SL_IBAT5+4(r1)
mtspr SPRN_IBAT5L,r4
lwz r4,SL_IBAT6(r1)
mtspr SPRN_IBAT6U,r4
lwz r4,SL_IBAT6+4(r1)
mtspr SPRN_IBAT6L,r4
lwz r4,SL_IBAT7(r1)
mtspr SPRN_IBAT7U,r4
lwz r4,SL_IBAT7+4(r1)
mtspr SPRN_IBAT7L,r4
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)

Expand Down

0 comments on commit ce32ed9

Please sign in to comment.