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Bug fix: Do not implement external memory interface if Platform start…
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…up is not selected. [ Bugzilla 1001590 ]
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vae committed May 18, 2012
1 parent 63fb8d4 commit 14b2fa1
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6 changes: 6 additions & 0 deletions packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog
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@@ -1,3 +1,9 @@
2012-05-17 Ilija Kocho <[email protected]>

* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
Bug fix: Do not implement external memory interface if Platform startup is
not selected. [ Bugzilla 1001590 ]

2012-02-25 Ilija Kocho <[email protected]>

* cdl/hal_cortexm_kinetis_twr_k70f120m.cdl:
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Expand Up @@ -56,17 +56,14 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M {
requires { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET)
implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" }

# implements CYGINT_HAL_CORTEXM4_CODE
# implements CYGINT_HAL_CORTEXM_FPV4_SP_D16
# implements CYGINT_HAL_CORTEXM_FPU_CODE
implements CYGINT_HAL_CACHE

requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 70 }
requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0" }
requires { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 }

implements CYGINT_IO_SERIAL_FREESCALE_UART2
implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM

implements CYGINT_HAL_FREESCALE_UART2
implements CYGINT_HAL_CORTEXM_KINETIS_RTC
implements CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1
Expand Down Expand Up @@ -138,15 +135,18 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M {
cdl_option CYGHWR_MEMORY_LAYOUT_PLF {
display "Memory layout by platform"
flavor data
active_if { CYG_HAL_STARTUP_PLF != "ByVariant" }
implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM
no_define
parent CYGHWR_MEMORY_LAYOUT
calculated {
(CYG_HAL_STARTUP_PLF == "ByVariant" ) ? 0 :
(CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" :
(CYG_HAL_STARTUP == "RAM") ? "kinetis_"
. CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_ram" :
(CYG_HAL_STARTUP == "ROM") ? "kinetis_"
. CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_rom" :
"undefined_by_PLF" }
"Error!"
}
description "
Combination of 'Startup type' and 'Kinetis member in use'
produces the memory layout."
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