target-i386: fix ordering of fields in CPUX86State

Make sure reset zeroes TSC_AUX, XCR0, PKRU. Move XSTATE_BV from the "vmstate only" section to the "KVM only" section. Signed-off-by: Paolo Bonzini <[email protected]>
prog012 · Sep 14, 2016 · 7616f1c · 7616f1c
1 parent bb93e09
commit 7616f1c
Showing 1 changed file with 6 additions and 6 deletions.
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
@@ -1035,6 +1035,9 @@ typedef struct CPUX86State {
     uint64_t tsc;
     uint64_t tsc_adjust;
     uint64_t tsc_deadline;
+    uint64_t tsc_aux;
+
+    uint64_t xcr0;
 
     uint64_t mcg_status;
     uint64_t msr_ia32_misc_enable;
@@ -1051,6 +1054,8 @@ typedef struct CPUX86State {
     uint64_t pat;
     uint32_t smbase;
 
+    uint32_t pkru;
+
     /* End of state preserved by INIT (dummy marker).  */
     struct {} end_init_save;
 
@@ -1135,20 +1140,15 @@ typedef struct CPUX86State {
     uint64_t mcg_ctl;
     uint64_t mcg_ext_ctl;
     uint64_t mce_banks[MCE_BANKS_DEF*4];
-
-    uint64_t tsc_aux;
+    uint64_t xstate_bv;
 
     /* vmstate */
     uint16_t fpus_vmstate;
     uint16_t fptag_vmstate;
     uint16_t fpregs_format_vmstate;
-    uint64_t xstate_bv;
 
-    uint64_t xcr0;
     uint64_t xss;
 
-    uint32_t pkru;
-
     TPRAccess tpr_access_type;
 } CPUX86State;