AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Real Digital Vivado IP Library

Create beautiful, publication-quality books and documents from computational content.

A showcase for Sphinx documentation themes

Verilog formatter

Raptor end-to-end FPGA Compiler and GUI

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

Files for Hackster project https://www.hackster.io/adam-taylor/fun-with-fusesoc-7b2b1d

Repository gathering basic modules for CDC purpose

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

FPGA display controller with support for VGA, DVI, and HDMI.

A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (p…

Example skywater tutorial

A project demonstrating how to use the OSVVM library and its Axi4LiteManager verification component to simulate an airhdl register bank.

A simple three-stage RISC-V CPU

A rudimental RISCV CPU supporting RV32I instructions, in VHDL

demo project to show how to use vivado tcl scripts to do everything.

ethos-u-vela is the ML model compiler tool and used to compile a TFLite-Micro model into an optimised version for ethos-u NPU on iMX93 platform

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Common elements for FPGA Design (FIFOs, RAMs, etc.)

🔊 Text-Prompted Generative Audio Model

🐸💬 - a deep learning toolkit for Text-to-Speech, battle-tested in research and production

Model Training for ADI's MAX78000 and MAX78002 Edge AI Devices

Python PID Tuning Suite

4 stage, in-order, secure RISC-V core based on the CV32E40P

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

An SSD1306 VHDL implementation written in Altera Quartus for my Cyclone IV development board

FPGA shared code for my projects