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[hardware] draft: refactor STU-exception flush engine
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@mp-17
mp-17 committed Jan 18, 2025
1 parent a4614b5 commit f2c522e
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Showing 8 changed files with 147 additions and 60 deletions.
15 changes: 12 additions & 3 deletions hardware/src/ara.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -184,6 +184,9 @@ module ara import ara_pkg::*; #(
logic [NrLanes-1:0] fflags_ex_valid;
logic [NrLanes-1:0] vxsat_flag;
vxrm_t [NrLanes-1:0] alu_vxrm;
// Flush support for store exceptions
logic stu_ex_flush_lane, stu_ex_flush_done;
logic [NrLanes-1:0] stu_ex_flush_stu;

ara_dispatcher #(
.NrLanes (NrLanes ),
Expand All @@ -210,6 +213,9 @@ module ara import ara_pkg::*; #(
.alu_vxrm_o (alu_vxrm ),
.fflags_ex_i (fflags_ex ),
.fflags_ex_valid_i (fflags_ex_valid ),
// Flush support
.stu_ex_flush_o (stu_ex_flush_lane),
.stu_ex_flush_done_i(stu_ex_flush_done),
// Interface with the Vector Store Unit
.core_st_pending_o (core_st_pending ),
.load_complete_i (load_complete ),
Expand Down Expand Up @@ -306,7 +312,6 @@ module ara import ara_pkg::*; #(
elen_t [NrLanes-1:0] stu_operand;
logic [NrLanes-1:0] stu_operand_valid;
logic [NrLanes-1:0] stu_operand_ready;
logic stu_exception_flush;
// Slide unit/address generation operands
elen_t [NrLanes-1:0] sldu_addrgen_operand;
target_fu_e[NrLanes-1:0] sldu_addrgen_operand_target_fu;
Expand Down Expand Up @@ -366,6 +371,9 @@ module ara import ara_pkg::*; #(
.alu_vxrm_i (alu_vxrm[lane] ),
.fflags_ex_o (fflags_ex[lane] ),
.fflags_ex_valid_o (fflags_ex_valid[lane] ),
// Support for store exception flush
.stu_ex_flush_i (stu_ex_flush_lane ),
.stu_ex_flush_o (stu_ex_flush_stu[lane] ),
// Interface with the sequencer
.pe_req_i (pe_req ),
.pe_req_valid_i (pe_req_valid ),
Expand Down Expand Up @@ -395,7 +403,6 @@ module ara import ara_pkg::*; #(
.stu_operand_o (stu_operand[lane] ),
.stu_operand_valid_o (stu_operand_valid[lane] ),
.stu_operand_ready_i (stu_operand_ready[lane] ),
.stu_exception_flush_i (stu_exception_flush ),
// Interface with the slide/address generation unit
.sldu_addrgen_operand_o (sldu_addrgen_operand[lane] ),
.sldu_addrgen_operand_target_fu_o(sldu_addrgen_operand_target_fu[lane]),
Expand Down Expand Up @@ -495,6 +502,9 @@ module ara import ara_pkg::*; #(
.load_complete_o (load_complete ),
.store_complete_o (store_complete ),
.store_pending_o (store_pending ),
// STU exception support
.stu_ex_flush_i (|stu_ex_flush_stu ),
.stu_ex_flush_done_o (stu_ex_flush_done ),
// Interface with the sequencer
.pe_req_i (pe_req ),
.pe_req_valid_i (pe_req_valid ),
Expand All @@ -515,7 +525,6 @@ module ara import ara_pkg::*; #(
.stu_operand_i (stu_operand ),
.stu_operand_valid_i (stu_operand_valid ),
.stu_operand_ready_o (stu_operand_ready ),
.stu_exception_flush_o (stu_exception_flush ),
// Address Generation
.addrgen_operand_i (sldu_addrgen_operand ),
.addrgen_operand_target_fu_i(sldu_addrgen_operand_target_fu ),
Expand Down
68 changes: 66 additions & 2 deletions hardware/src/ara_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
// Interface with the lanes
input logic [NrLanes-1:0][4:0] fflags_ex_i,
input logic [NrLanes-1:0] fflags_ex_valid_i,
// STU exception-related flush support
output logic stu_ex_flush_o,
input logic stu_ex_flush_done_i,
// Rounding mode is shared between all lanes
input logic [NrLanes-1:0] vxsat_flag_i,
output vxrm_t [NrLanes-1:0] alu_vxrm_o,
Expand Down Expand Up @@ -141,6 +144,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
typedef enum logic [1:0] {
NORMAL_OPERATION,
WAIT_IDLE,
WAIT_IDLE_FLUSH,
RESHUFFLE
} state_e;
state_e state_d, state_q, state_qq;
Expand Down Expand Up @@ -289,6 +293,53 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
.ara_resp_valid_o(ara_resp_valid)
);

// STU exception flush FSM
// Upon exception, Ara should be flushed as soon as no operations older than the store are ongoing.
// For this reason, we should first wait until Ara is idle. Then, we can flush.
logic stu_ex_flush_start, stu_ex_flush_done, stu_ex_flush_done_q;
typedef enum logic [1:0] {
STU_FLUSH_IDLE,
STU_FLUSH,
STU_FLUSH_WAIT,
STU_FLUSH_DONE
} stu_ex_flush_fsm_e;
stu_ex_flush_fsm_e stu_ex_state_d, stu_ex_state_q;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
stu_ex_state_q <= STU_FLUSH_IDLE;
stu_ex_flush_done_q <= 1'b0;
end else begin
stu_ex_state_q <= stu_ex_state_d;
stu_ex_flush_done_q <= stu_ex_flush_done_i;
end
end

always_comb begin : i_stu_ex_flush_fsm
stu_ex_state_d = stu_ex_state_q;
stu_ex_flush_o = 1'b0;
stu_ex_flush_done = 1'b0;

case (stu_ex_state_q)
STU_FLUSH_IDLE: begin
if (stu_ex_flush_start)
stu_ex_state_d = STU_FLUSH;
end
STU_FLUSH: begin
stu_ex_flush_o = 1'b1;
stu_ex_state_d = STU_FLUSH_WAIT;
end
STU_FLUSH_WAIT: begin
if (stu_ex_flush_done_q)
stu_ex_state_d = STU_FLUSH_DONE;
end
STU_FLUSH_DONE: begin
stu_ex_flush_done = 1'b1;
stu_ex_state_d = STU_FLUSH_IDLE;
end
endcase
end

///////////////
// Decoder //
///////////////
Expand Down Expand Up @@ -386,6 +437,19 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
if (ara_idle_i) state_d = NORMAL_OPERATION;
end

// Wait for idle and then flush the stu-related pipes.
// This operation is not IPC critical.
WAIT_IDLE_FLUSH: begin
if (ara_idle_i) begin
// Start the flush FSM
stu_ex_flush_start = 1'b1;
end
// Get back to normal operation once the flush is over
if (stu_ex_flush_done) begin
state_d = NORMAL_OPERATION;
end
end

// Inject a reshuffle instruction
RESHUFFLE: begin
// Instruction is of one of the RVV types
Expand Down Expand Up @@ -3237,10 +3301,10 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
acc_resp_o.exception = ara_resp.exception;
ara_req_valid = 1'b0;
// In case of exception, modify vstart and wait until the previous
// operations are over
// operations are over. Then, flush.
if ( ara_resp.exception.valid ) begin
csr_vstart_d = ara_resp.exception_vstart;
state_d = WAIT_IDLE;
state_d = WAIT_IDLE_FLUSH;
end
end
ara_req.eew_vs1 = ara_req.vtype.vsew; // This is the new vs1 EEW
Expand Down
35 changes: 20 additions & 15 deletions hardware/src/lane/lane.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
input vxrm_t alu_vxrm_i,
output logic [4:0] fflags_ex_o,
output logic fflags_ex_valid_o,
// Support for store exception flush
input logic stu_ex_flush_i,
output logic stu_ex_flush_o,
// Interface with the sequencer
input `STRUCT_PORT_BITS(pe_req_t_bits) pe_req_i,
input logic pe_req_valid_i,
Expand All @@ -61,7 +64,6 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
output elen_t stu_operand_o,
output logic stu_operand_valid_o,
input logic stu_operand_ready_i,
input logic stu_exception_flush_i,
// Interface with the Slide/Address Generation unit
output elen_t sldu_addrgen_operand_o,
output target_fu_e sldu_addrgen_operand_target_fu_o,
Expand Down Expand Up @@ -220,6 +222,10 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
// Interface with the MaskB operand queue (VRGATHER/VCOMPRESS)
logic mask_b_cmd_pop;

// Support for store exception flush
logic stu_ex_flush_op_req_d, stu_ex_flush_op_req_q;
`FF(stu_ex_flush_op_req_q, stu_ex_flush_op_req_d, 1'b0, clk_i, rst_ni);

// Additional signals to please Verilator's hierarchical verilation
pe_req_t pe_req;
pe_resp_t pe_resp;
Expand All @@ -242,6 +248,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.pe_vinsn_running_i (pe_vinsn_running_i ),
.pe_req_ready_o (pe_req_ready_o ),
.pe_resp_o (pe_resp ),
// Support for store exception flush
.stu_ex_flush_i (stu_ex_flush_i ),
.stu_ex_flush_o (stu_ex_flush_op_req_d),
// Interface with the operand requesters
.operand_request_o (operand_request ),
.operand_request_valid_o(operand_request_valid),
Expand Down Expand Up @@ -296,6 +305,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
logic mfpu_result_gnt;
// To the slide unit (reductions)
logic sldu_result_gnt_opqueues;
// Support for store exception flush
logic stu_ex_flush_op_queues_d, stu_ex_flush_op_queues_q;
`FF(stu_ex_flush_op_queues_q, stu_ex_flush_op_queues_d, 1'b0, clk_i, rst_ni);

operand_requester #(
.NrLanes (NrLanes ),
Expand All @@ -313,6 +325,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.operand_request_i (operand_request ),
.operand_request_valid_i (operand_request_valid ),
.operand_request_ready_o (operand_request_ready ),
// Support for store exception flush
.stu_ex_flush_i (stu_ex_flush_op_req_q ),
.stu_ex_flush_o (stu_ex_flush_op_queues_d),
// Interface with the VRF
.vrf_req_o (vrf_req ),
.vrf_addr_o (vrf_addr ),
Expand Down Expand Up @@ -363,9 +378,7 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.ldu_result_wdata_i (ldu_result_wdata_i ),
.ldu_result_be_i (ldu_result_be_i ),
.ldu_result_gnt_o (ldu_result_gnt_o ),
.ldu_result_final_gnt_o (ldu_result_final_gnt_o ),
// Store Unit
.stu_exception_i ( stu_exception_flush_i )
.ldu_result_final_gnt_o (ldu_result_final_gnt_o )
);

////////////////////////////
Expand Down Expand Up @@ -414,16 +427,6 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
logic sldu_operand_opqueues_ready;
logic sldu_addrgen_operand_opqueues_valid;

// Cut stu_exception path
logic stu_exception_flush;
logic [StuExLat:0] stu_exception_flush_d, stu_exception_flush_q;
assign stu_exception_flush_d[0] = stu_exception_flush_i;
assign stu_exception_flush = StuExLat == 0 ? stu_exception_flush_i : stu_exception_flush_q[StuExLat-1];
for (genvar i = 0; i < StuExLat; i++) begin
assign stu_exception_flush_d[i+1] = stu_exception_flush_q[i];
`FF(stu_exception_flush_q[i], stu_exception_flush_d[i], 1'b0, clk_i, rst_ni);
end

operand_queues_stage #(
.NrLanes (NrLanes ),
.VLEN (VLEN ),
Expand All @@ -441,6 +444,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.operand_queue_ready_o (operand_queue_ready ),
.operand_queue_cmd_i (operand_queue_cmd ),
.operand_queue_cmd_valid_i (operand_queue_cmd_valid ),
// Support for store exception flush
.stu_ex_flush_i (stu_ex_flush_op_queues_q ),
.stu_ex_flush_o (stu_ex_flush_o ),
// Interface with the Lane Sequencer
.mask_b_cmd_pop_o (mask_b_cmd_pop ),
// Interface with the VFUs
Expand All @@ -456,7 +462,6 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.stu_operand_o (stu_operand_o ),
.stu_operand_valid_o (stu_operand_valid_o ),
.stu_operand_ready_i (stu_operand_ready_i ),
.stu_exception_flush_i (stu_exception_flush ),
// Address Generation Unit
.sldu_addrgen_operand_o (sldu_addrgen_operand_opqueues ),
.sldu_addrgen_operand_target_fu_o (sldu_addrgen_operand_target_fu_o ),
Expand Down
13 changes: 12 additions & 1 deletion hardware/src/lane/lane_sequencer.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,9 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
input logic [NrVInsn-1:0] pe_vinsn_running_i,
output logic pe_req_ready_o,
output pe_resp_t pe_resp_o,
// Support for store exception flush
input logic stu_ex_flush_i,
output logic stu_ex_flush_o,
// Interface with the operand requester
output operand_request_cmd_t [NrOperandQueues-1:0] operand_request_o,
output logic [NrOperandQueues-1:0] operand_request_valid_o,
Expand All @@ -46,6 +49,11 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
input vrgat_req_t masku_vrgat_req_i
);

`include "common_cells/registers.svh"

// STU exception support
`FF(stu_ex_flush_o, stu_ex_flush_i, 1'b0, clk_i, rst_ni);

////////////////////////////
// Register the request //
////////////////////////////
Expand All @@ -70,7 +78,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
) i_pe_req_register (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.clr_i (1'b0 ),
.clr_i (stu_ex_flush_o ),
.testmode_i(1'b0 ),
.data_i (pe_req_i ),
.valid_i (pe_req_valid_i_msk),
Expand Down Expand Up @@ -147,6 +155,9 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
operand_request_valid_d[queue] = 1'b1;
end
end

// Flush upon store
if (stu_ex_flush_o) operand_request_valid_d[StA] = 1'b0;
end

always_ff @(posedge clk_i or negedge rst_ni) begin: p_operand_request_ff
Expand Down
14 changes: 11 additions & 3 deletions hardware/src/lane/operand_queues_stage.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,9 @@ module operand_queues_stage import ara_pkg::*; import rvv_pkg::*; import cf_math
output logic [NrOperandQueues-1:0] operand_queue_ready_o,
input operand_queue_cmd_t [NrOperandQueues-1:0] operand_queue_cmd_i,
input logic [NrOperandQueues-1:0] operand_queue_cmd_valid_i,
// Support for store exception flush
input logic stu_ex_flush_i,
output logic stu_ex_flush_o,
// Interface with the Lane Sequencer
output logic mask_b_cmd_pop_o,
// Interface with the VFUs
Expand Down Expand Up @@ -52,6 +55,11 @@ module operand_queues_stage import ara_pkg::*; import rvv_pkg::*; import cf_math
input logic [1:0] mask_operand_ready_i
);

`include "common_cells/registers.svh"

// STU flush support
`FF(stu_ex_flush_o, stu_ex_flush_i, 1'b0, clk_i, rst_ni);

///////////
// ALU //
///////////
Expand Down Expand Up @@ -218,7 +226,7 @@ module operand_queues_stage import ara_pkg::*; import rvv_pkg::*; import cf_math
) i_operand_queue_st_mask_a (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.flush_i (stu_exception_flush_i ),
.flush_i (stu_ex_flush_o ),
.lane_id_i (lane_id_i ),
.operand_queue_cmd_i (operand_queue_cmd_i[StA] ),
.operand_queue_cmd_valid_i(operand_queue_cmd_valid_i[StA]),
Expand Down Expand Up @@ -263,7 +271,7 @@ module operand_queues_stage import ara_pkg::*; import rvv_pkg::*; import cf_math
) i_operand_queue_slide_addrgen_a (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.flush_i (1'b0 ),
.flush_i (stu_ex_flush_o ),
.lane_id_i (lane_id_i ),
.operand_queue_cmd_i (operand_queue_cmd_i[SlideAddrGenA] ),
.operand_queue_cmd_valid_i(operand_queue_cmd_valid_i[SlideAddrGenA] ),
Expand Down Expand Up @@ -321,7 +329,7 @@ module operand_queues_stage import ara_pkg::*; import rvv_pkg::*; import cf_math
) i_operand_queue_mask_m (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.flush_i (1'b0 ),
.flush_i (stu_ex_flush_o ),
.lane_id_i (lane_id_i ),
.operand_queue_cmd_i (operand_queue_cmd_i[MaskM] ),
.operand_queue_cmd_valid_i(operand_queue_cmd_valid_i[MaskM]),
Expand Down
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