A Verilog RNN Library I made for CS8803ACT. Intending to make Python wrapper later on.
- note to self: clean up this project with newly-learned verilog/vhdl organization skills
- add my class presentations/architecture/etc to this repo
- by the time I get around to cleaning this up there will probably be new recommended activation functions. So add those too.
Old Run Instructions (needs to be updated)
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Open Quartus Project File "rnn.qpf" in Quartus Prime Lite
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set rnn_cell as top level design if not already
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double click Analysis & Synthesis
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open RTL viewer to see design
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open the plus signs in upper left to see underlying designs
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use project navigator => files to see the Verilog and explore files/functional tests
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set smaller modules as Top Level Entity to synthesize that and test it if desired