Commits

Branch selector

 master

User selector

nhaehnle

Datepicker

All time

Commit History

Commits on Nov 28, 2017

• AMDGPU: Re-organize the outer loop of SILoadStoreOptimizer

  Show description for f62da81
  nhaehnle

  committed
  f62da81

  Copy full SHA for f62da81

• AMDGPU: Consistently check for immediates in SIInstrInfo::FoldImmediate

  Show description for f884784
  nhaehnle

  committed
  f884784

  Copy full SHA for f884784

Commits on Nov 22, 2017

• AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOptimizer

  Show description for 72bc6f1
  nhaehnle

  committed
  72bc6f1

  Copy full SHA for 72bc6f1

Commits on Oct 10, 2017

• AMDGPU: Split MUBUF offset into aligned components

  Show description for 73de2f1
  nhaehnle

  committed
  73de2f1

  Copy full SHA for 73de2f1

Commits on Sep 29, 2017

• AMDGPU: fix bad test exposed by r314522

  Show description for 80d2bc6
  nhaehnle

  committed
  80d2bc6

  Copy full SHA for 80d2bc6

• AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC

  Show description for da47d9d
  nhaehnle

  committed
  da47d9d

  Copy full SHA for da47d9d

Commits on Sep 6, 2017

• AMDGPU: Make worst-case assumption about the wait states in inline assembly

  Show description for adf1cb6
  nhaehnle

  committed
  adf1cb6

  Copy full SHA for adf1cb6

Commits on Sep 1, 2017

• AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states

  Show description for 96b6414
  nhaehnle

  committed
  96b6414

  Copy full SHA for 96b6414

Commits on Jul 18, 2017

• AMDGPU: Fix crash when folding immediates into multiple uses

  Show description for 78554e8
  nhaehnle

  committed
  78554e8

  Copy full SHA for 78554e8

Commits on Jun 27, 2017

• AMDGPU: M0 operands to spill/restore opcodes are dead

  Show description for 7ca3576
  nhaehnle

  committed
  7ca3576

  Copy full SHA for 7ca3576

Commits on Apr 24, 2017

• AMDGPU: Move v_readlane lane select from VGPR to SGPR

  Show description for c3187b4
  nhaehnle

  committed
  c3187b4

  Copy full SHA for c3187b4

• InstCombine/AMDGPU: Fix constant folding of llvm.amdgcn.{icmp,fcmp}

  Show description for 7b717b6
  nhaehnle

  committed
  7b717b6

  Copy full SHA for 7b717b6

• AMDGPU: Fix crash when scheduling non-memory SMRD instructions

  Show description for 1c1f7ef
  nhaehnle

  committed
  1c1f7ef

  Copy full SHA for 1c1f7ef

Commits on Jan 31, 2017

• [DAGCombine] require UnsafeFPMath for re-association of addition

  Show description for ab43652
  nhaehnle

  committed
  ab43652

  Copy full SHA for ab43652

Commits on Dec 12, 2016

• AMDGPU: llvm.amdgcn.interp.mov is a source of divergence

  Show description for ddba2a5
  nhaehnle

  committed
  ddba2a5

  Copy full SHA for ddba2a5

Commits on Dec 8, 2016

• [SelectionDAG] Add expansion and promotion of [US]MUL_LOHI

  Show description for 616da7e
  nhaehnle

  committed
  616da7e

  Copy full SHA for 616da7e

• X86: Add checks for fma_patterns[_wide].ll with -enable-no-infs-fp-math

  Show description for 09d35d9
  nhaehnle

  committed
  09d35d9

  Copy full SHA for 09d35d9

• AMDGPU: Properly implement SIRegisterInfo::isFrameOffsetLegal and needsFrameBaseReg

  Show description for e299df1
  nhaehnle

  committed
  e299df1

  Copy full SHA for e299df1

Commits on Dec 2, 2016

• [DAGCombiner] do not fold (fmul (fadd X, 1), Y) -> (fmad X, Y, Y) by default

  Show description for 42285f5
  nhaehnle

  committed
  42285f5

  Copy full SHA for 42285f5

Commits on Dec 1, 2016

• [SelectionDAG] Rename and clarify visitFMULForFMADCombine (NFC)

  Show description for 77151a0
  nhaehnle

  committed
  77151a0

  Copy full SHA for 77151a0

Commits on Nov 30, 2016

• [SelectionDAG] Refactor TargetLowering::expandMUL (NFC)

  Show description for 989c694
  nhaehnle

  committed
  989c694

  Copy full SHA for 989c694

Commits on Nov 23, 2016

• [SelectionDAG] Early-out in TargetLowering::expandMUL (NFC)

  Show description for da8f0a5
  nhaehnle

  committed
  da8f0a5

  Copy full SHA for da8f0a5

Commits on Nov 18, 2016

• AMDGPU: Fix legalization of MUBUF instructions in shaders

  Show description for 1e27a61
  nhaehnle

  committed
  1e27a61

  Copy full SHA for 1e27a61

Commits on Nov 3, 2016

• DAGCombiner: fix use-after-free when merging consecutive stores

  Show description for de5ede6
  nhaehnle

  committed
  de5ede6

  Copy full SHA for de5ede6

Commits on Nov 2, 2016

• AMDGPU: Allow additional implicit operands on MOVRELS instructions

  Show description for 08f7b24
  nhaehnle

  committed
  08f7b24

  Copy full SHA for 08f7b24

Commits on Oct 27, 2016

• AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged due register dependencies

  Show description for ce0a523
  nhaehnle

  committed
  ce0a523

  Copy full SHA for ce0a523

Commits on Oct 24, 2016

• AMDGPU: Fix Two Address problems with v_movreld

  Show description for e07033a
  nhaehnle

  committed
  e07033a

  Copy full SHA for e07033a

Commits on Oct 14, 2016

• AMDGPU: Select 64-bit {ADD,SUB}{C,E} nodes

  Show description for 877e3be
  nhaehnle

  committed
  877e3be

  Copy full SHA for 877e3be

• Fix use-after-frees

  Show description for 9b21983
  nhaehnle

  committed
  9b21983

  Copy full SHA for 9b21983

• AMDGPU: Fix use-after-frees

  Show description for 5d66203
  nhaehnle

  committed
  5d66203

  Copy full SHA for 5d66203

Commits on Oct 7, 2016

• AMDGPU: Fix use-after-free in SIOptimizeExecMasking

  Show description for f3907ed
  nhaehnle

  committed
  f3907ed

  Copy full SHA for f3907ed

Commits on Sep 12, 2016

• AMDGPU: Do not clobber SCC in SIWholeQuadMode

  Show description for 01a133c
  nhaehnle

  committed
  01a133c

  Copy full SHA for 01a133c

Commits on Sep 3, 2016

• AMDGPU: Reduce the duration of whole-quad-mode

  Show description for f9f3b70
  nhaehnle

  committed
  f9f3b70

  Copy full SHA for f9f3b70

• AMDGPU: Fix an interaction between WQM and polygon stippling

  Show description for c280d74
  nhaehnle

  committed
  c280d74

  Copy full SHA for c280d74

Commits on Aug 17, 2016

• LiveIntervals: add removeRegUnit

  Show description for 6811218
  nhaehnle

  committed
  6811218

  Copy full SHA for 6811218

Pagination

Previous

Next